Lyndsy

Lyndsy posted an update 5 years, 1 month ago · , 0, 0

Tips of Using Vivado on Win8

Installed Vivado 14.4 on Win8 today. Win8 doesn’t have start menu. At the beginning I didn’t even know how to launch Vivado. Figured it out finally: go to where Vivardo is installed, say, C:XilinxVivado2014.4binunwrappedwin64.o; then create a shortcut for…[Read more]
Lyndsy posted in ASIC and FPGA 5 years, 2 months ago · , 1, 1

Generate RTL code from Python

Bumped into MyHDL website, http://old.myhdl.org/doku.php, today. It offers MyHDL, an open source Python package, that allows users to use Python as hardware description and verification language. Users can convert Python codes into Verilog or VHDL.…[Read more]

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Lyndsy replied to the topic DDR DQS and DQ Timing in the forum ASIC and FPGA 5 years, 2 months ago · , 0, 0

For read, controller PHY will delay DQS by 90° so that DQS toggles right in the middle of DQ.

For write, yes, DDR samples DQ at DQS toggling edges.