Lack of signal force support in VHDL is really a headache to verification engineers. Unfortunately I ran into this issue recently. A signal in VHDL has to be forced in test bench or I have to hack VHDL which is obviously not desired. Amid quite a bit…[Read more]
I use VHDL. The following is a short slides about delta delay in VHDL. I think basically assigning to signals using <= introduces delta delay while assign to variable using := does not. Not sure about Verilog. I heard it also has delta delay.
Kliang, how about you also add delta delay to the clock of the launching FF? So launching FF clock is one delta delayed version of the original clock so its clock edge is perfectly aligned with latching FF clock edge. In other words, all FF’s clocks have the same delta delay.