• echatterjee posted an update 1 year, 6 months ago  · , 0, 0

    #SV #assertion

    See a assertion like below:

    property check_trig (rstn, state, trig);
    disable iff(!rstn) (state === STATE_PRE) |-> #[1,3] (trig == 0x1);
    endproperty

    Understand it tries to say if not in reset and state is STATE_PRE, trig is supposed to be 1. But confused what #[1,3] means. It turns out it means within 1 to 3 clock cycles and the clock is defined where this property is called.

    Good sv assertion tutorial from Doulos.