-
earnestwu replied to the topic Verilog test BFM to drive and monitor internal AHB bus in the forum
ASIC and FPGA 4 years, 5 months ago · , 0, 0
I see. Thanks.
Normally force/release are used as a pair. I don’t see release is used in above so test bench drives the internal signal all the time. I think it is good.
Along the line of using assignment, I think we can use ifdef in RTL. Idea is if a string is defined, internal RTL…[Read more]
-
earnestwu started the topic Verilog test BFM to drive and monitor internal AHB bus in the forum
ASIC and FPGA 4 years, 5 months ago · , 0, 0
We have a design with an embedded arm processor. We can do software-hardware co-sim and run simple c test code on arm processor. But we’d like to have another way which we can bypass (sort of disconnect) arm processor and use a TB BFM to drive AHB bus. Note we don’t want to touch rtl code.…[Read more]
-
earnestwu started the topic Run multiple tests out of the same modelsim compiled work library? in the forum
ASIC and FPGA 4 years, 5 months ago · , 0, 0
It takes time to recompile. So is it possible to run multiple RTL test cases out of the same modelsim work library? Actually is it the way how we setup multiple test cases environment since we don’t want to compile all rtl+tb per each test case?
-
earnestwu started the topic Ring Oscillator in FPGA? in the forum
ASIC and FPGA 4 years, 10 months ago · , 0, 0
// LSO: Latch Synchronized Oscillator
module lso (nrst, osc, aclk);
input nrst;
output osc, aclk;wire a1, a2;
wire trig_en;
wire clk;
reg clk_div2;siro s1 (nrst, osc);
assign trig_en = a1 ^ a2;
assign clk = trig_en & osc;
assign a1 = ~(nrst & clk_div2);
assign a2 = nrst &…[Read more] -
earnestwu commented on the post, [Matlab] GPS Acquisition Simple Implementation 4 years, 10 months ago · , 0, 0
Code works. Some explaining or doc can be better.
-
earnestwu commented on the post, Apply Cordic Algorithm to Digital FM Receiver 4 years, 10 months ago · , 0, 0
Good presentation using cordic in FM recv signal processing and FM demod. Even a good tutorial on how FM works. Well worth the points I hard earned.
-
earnestwu commented on the post, Use Cordic to Implement DDS with Verilog Code 4 years, 10 months ago · , 0, 0
Thanks! The code all works on my side. Good reference to get me started using Cordic.
earnestwu posted an update 1 year, 4 months ago · , 0, 0
FIB for 20nm chip
Recently need to do FIB to a 20nm chip. An inverter needs to be bypassed. Faced questions such as backside FIB or frontside FIB, FIB can only cut wire and can not grow wire, etc.
Find below doc very helpful and would like to share…[Read more]
earnestwu posted an update 2 years, 10 months ago · , 0, 0
#git
git is a widely adopted version control toolset. Some tips.
If you have a file locally changed and you want to merge with latest/HEAD in repo before add and commit to local repo, you can do
git stash
git pull
git stash pop
git stash pop will do merge for you.
If your local change…[Read more]
earnestwu posted an update 2 years, 10 months ago · , 0, 0
#Verilog, Part-select or indexed part-select cannot be applied to memory
Very annoying Verilog compiling error. Do you see anything wrong in below?
assign smpl_data[2:1] = 2’b0;
assign smpl_data[0] = 1’b1;
Turns out in some version of Verilog compile such as ncsim it is not allowed.…[Read more]