earnestwu

FIB for 20nm chip

Recently need to do FIB to a 20nm chip. An inverter needs to be bypassed. Faced questions such as backside FIB or frontside FIB, FIB can only cut wire and can not grow wire, etc.

Find below doc very helpful and would like to share…[Read more]

#git

git is a widely adopted version control toolset. Some tips.

If you have a file locally changed and you want to merge with latest/HEAD in repo before add and commit to local repo, you can do
git stash
git pull
git stash pop

git stash pop will do merge for you.

If your local change…[Read more]

#Verilog, Part-select or indexed part-select cannot be applied to memory

Very annoying Verilog compiling error. Do you see anything wrong in below?
assign smpl_data[2:1] = 2’b0;
assign smpl_data[0] = 1’b1;

Turns out in some version of Verilog compile such as ncsim it is not allowed.…[Read more]