Get reset domain crossing RDC right. Mentor webinar.
A new breed of domain crossings introduce challenging issues, including those related to metastability, in the design of ASICs. These #reset domain crossings (RDC) have become more prevalent due to the increase of third party IP,…[Read more]
The #RISC-V ISA has pursued minimalism to a fault.
There is a large emphasis on minimizing instruction count, normalizing encoding, etc. This pursuit of minimalism has resulted in false orthogonalities (such as reusing the same instruction for branches, calls and returns) and a…[Read more]
I am a first year ECE master student and currently am doing summer intern in a startup. They ask me to do verification for some digital blocks. It is sort of old school since their verification env is based on Verilog and a little bit C for…[Read more]
I know we can use timescale to define the desired simulation resolution in a Verilog file. But timescale can be put anywhere. For example, top module defines 1ps, top/sub defines 2ps, top/sub/sub defines 3ps, and so on. How do I know exactly what resolution is used in simulation with so…[Read more]
Good article and scripts. There are many discussions about how to write TB but few about setting up a scalable test env such as where to hold rtl, common tb code, specific test case code, rtl/tb file list, test case list, where to hold test case data, how to do test automation, etc. This…[Read more]
So the goal is for rtl designer to improve productivity by working at higher abstraction level or for other designers like software Java programmers or lab test guys to be able to write rtl code? If latter, it is just a niche application case and bottom line is they can always learn systemverilog?