DougSlingerland

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In ASIC/SOC Which Area is More Promising for Young Chip Engineers

Start: 01/12/2016
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In ASIC/SOC Which Area is More Promising for Young Chip Engineers

Promising Areas

Simulation and Verification
SOC Integration
SOC IP Design
DFT
Backend PrimeTime and Synthesis
Backend Place and Routing
Others

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Comments and Q&As

DougSlingerland commented on the post, PTPX Peak Power 3 years ago · , 0, 0

In the report, clock network consumes 19% pwr. Is it typical or a little bit high?

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DougSlingerland commented on the post, Basics of At-Speed DFT test 3 years ago · , 0, 0

Glad to realize there is both at speed shift and at speed capture.

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