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Arcis posted an update 1 month, 2 weeks ago · , 0, 0
Standard cell reading:
Arcis posted in ASIC and FPGA 1 month, 2 weeks ago · , 0, 1
Designing and Benchmarking of Double-Row Height Standard Cells
Still not sure why “Note that a double-row height cell uses M2 P/G rails rather than M1 P/G rails. The reason for this is “. But a good reading for #standardcell.
Double height cells can use the
region underneath the P/G rail…[Read more]
Arcis posted in MCU and DSP 5 months, 2 weeks ago · , 0, 1
Microchip Technology Video: First RISC-V SoC FPGA For Real-Time With Linux
4 reasons to use #RISC-V for #aerospace and defense applications
designers can then perform a full inspection of the RTL, providing confirmation of no malicious intent and establishing trust.
open source, no fee
Arcis posted in MCU and DSP 9 months ago · , 0, 1
Keynote, design thr next billion chips, how #risc-v is revolutionizing thd hardware
From sifive cofounder and cto
Arcis posted in IoT and Smart Devices 1 year, 9 months ago · , 0, 0
Top IoT applications and stories in 2017
Arcis posted in Car Electronics 3 years, 3 months ago · , 0, 0
NXP, Tongji Univ, SAIC and partners start large-scale road test for connected vehicles in China
It utilizes NXP’s RoadLINK solution, which is based on IEEE 802.11p instead of “slower and less reliable cellular networks” for vehicle-to-vehicle and vehicle-to-infrastructure (V2X)…[Read more]
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Arcis commented on the post, About Cross-Clock Domain Synchronization 1 year, 10 months ago · , 0, 0
So for slow clk, can use 1st ff out directly. It is also process dependant. Each process needs to calculate fail rate to chech 2 ff synchronizer works or not
To the point digest.
Arcis started the topic How this Incentia white papter about AOCV gets four/eight derating tables? in the forum IC Backend 3 years, 4 months ago · , 0, 0
Incentia has an interesting whitepaper about AOCV.
On page 5, it says four derating table for single mode and on page 7 eight derating tables for dual mode. I don’t follow. Any idea, anyone?
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