Don’t forget to swap memory behavioral model with #Xilinx #Coregen model when do FPGA synthesis
An intern wrote a small block. When synthesize the whole design with this new block using Xilinx #Vivado, it take way longer time to finish. It turns out his block has a big size memory. He…[Read more]
We use Xilinx Virtex6 FPGA to build an GTH based PCIe card. Connected to PC. Most of time PC device manager can detect this card with device ID and vendor ID but see no resource. We used IO space. Changed it to memory space and no help. Software…[Read more]
I use vcs and not modelsim. But the same also works on vcs. Use
to generate an encrypted vp file for simulation. design.v needs to have `protected and `endprotected as mentioned by chriszhou.