Members

Make it to the Right and Larger Audience

  • chennai
    fpga rtl cdc lint upf synthesis

  • Irvine, CA

  • ASIC, FPGA, DFT, Synthesis, Timing, PNR

  • Master student
    LA, CA
    Master
    ASIC, FPGA, Digital, Analog, PCB, Firmware

    - "AXI vs AHB performance simulation and comparison in the article, ahb and axi have similar latency and throughout but ahb is configured as 128b@400Mhz and axi as 64b@200Mhz. so axi is 4x ahb performance?!"View
  • Senior Engineer
    Irvine CA
    MSEE
    ASIC, FPGA, digital design

  • Engineer
    Los Angeles, CA
    Master ECE
    FPGA and PCB Board Design

  • Profile picture of SD-RTL-DGN
    San Diego, CA

    - "Remember you can synthesize a design with waveform to achieve low power Synopsys has Power Compiler introduced for years. It takes in simulation waveform and synthesizes a design to achieve low power based on […]"View
  • Electrical Engineer
    Irvine CA
    MSEE
    RTL Design, FPGA, Digital Design, Board Lab Bring-up

  • Engineer
    New York, NY
    Master
    Embedded, FPGA, Firmware, Control, PCB

  • Staff Engineer
    San Diego, CA
    MSEE
    FPGA, RTL, IP, Audio, Image, Video

  • Electrical Engineer
    Irvine CA
    Master
    Board Design, Firmware, ASIC, FPGA

  • Staff Engineer
    Irvine CA
    MSEE
    ASIC, FPGA, Digital Design, Board

  • Staff Engineer
    San Diego, CA
    MSEE
    FPGA design, digital design, embeded system

  • Senior Engineer
    TI
    Dallas, TX
    MSEE
    ASIC, FPGA, RTL

  • Member of Technical Staff
    CA
    MSEE
    ASIC and FPGA, circuit, embedded

    - "MIPI Introduces I3C for Sensor Connection Today we normally use I2C, SPI, etc. to connect sensors to MCU chip as shown in fig1. Lots of signals. MIPI introduces I3C to reduce signal count and I3C features include […]"View
  • Senior Staff Engineer
    MSEE
    ASIC, FPGA, Digital Design and Verificaiton

  • Staff Engineer I
    Irvine CA
    Master ECE
    FPGA, Embedded, RTOS

    - "Qualcomm Snapdragon 845 with booted performance for AI and VR Do we have applications to use smart phone processing power to process big data for AI?"View
  • Senior Engineer
    Qualcomm, Inc
    San Diego, CA
    MSEE
    FPGA, ASIC, digital design

  • Staff Enginer
    Intel
    San Diego, CA
    MSEE
    FPGA, ASIC

  • Staff hardware engineer
    San Jose, CA
    MSEE
    ASIC, FPGA, VLSI, IP

  • Staff Hardware Engineer
    Irvine, CA
    Master
    FPGA, ASIC IP, PCB, Embedded

  • Electrical Engineer
    San Diego, CA
    ASIC,FPGA

  • Profile picture of najjarl
    San Jose, California
    Robotics, FPGA, IoT, Machine Learning, Industrial Equipment, Optics,

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