Many Good Online Radio and Mixed Signal Papers and Thesis from Prof. Ian Galton and his Students

Make it to the Right and Larger Audience

Blog

Many Good Online Radio and Mixed Signal Papers and Thesis from Prof. Ian Galton and his Students

 

Thesis from his students: http://petrified.ucsd.edu/~ispg-adm/people.php

  Current Employment Thesis
Christian Venerus

PhD (2013)

 

Qualcomm Delta-Sigma FDC Based Fractional-N PLLs with Multi-Rate Quantizing Dynamic Element Matching
Nevena Rakuljic

PhD (2012)

 

Analog Devices A Generalized Tree-Structured DEM DAC and Enhanced Harmonic Distortion Correction in Pipelined ADCs
Gerry Taylor

PhD (2011)

 

Analog Devices Mostly Digital ADCs for Highly-Scaled CMOS Processes
Kevin Wang

PhD (2010)

 

Qualcomm Spur Reduction Techniques for Fractional-N PLLs

 

Andrea Panigada

PhD (2009)

 

Co-Founder, Linear Silicon Solutions (now Microchip Technology) Harmonic Distortion Correction in Pipelined Analog to Digital Converters
Kok-Lim Chan

PhD (2007)

 

MaxLinear High Speed, High Resolution Digital-to-Analog Converters
Ash Swaminathan

PhD (2006)

 

Qualcomm Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers
Eric Siragusa

PhD (2004)

 

Analog Devices Digitally Enhanced High Resolution Pipelined Analog-to-Digital Conversion
Sheng Ye

PhD (2003)

 

Co-Founder, MaxLinear Phase Realignment and Phase Noise Suppression in PLLs and DLLs

 

Jared Welz

PhD (2002)

 

Broadcom The Analysis and Design of Mismatch Shaping Digital-to-Analog Converters
Sudhakar Pamarti

PhD (2002)

 

Associate Professor, UCLA Enabling Techniques for Wide Bandwidth Fractional-N Phase Locked Loops
Eric Fogleman

PhD (2000)

 

MaxLinear Enabling Techniques for High-Resolution Analog-to-Digital Conversion in IC Fabrication Processes Optimized for Digital Circuits
Henrik Jensen

PhD (1997)

 

Broadcom Analyses of Dynamic Element Matching Techniques for Data Conversion

 

Papers from Prof. Galton: http://petrified.ucsd.edu/~ispg-adm/publications.php

 

C. Weltin-Wu, G. Zhao, I. Galton, “A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion,” IEEE Journal of Solid State Circuits, vol. 50, no. 12, pp. 2988 – 3002, December 2015.
C. Venerus, I. Galton, “Quantization Noise Cancellation for FDC-Based Fractional-N PLLs,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 62, no. 12, pp. 1119 – 1123, December 2015.
C. Weltin-Wu, E. Familier, I. Galton, “A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs,” IEEE Transactions of Signals and Systems I: Regular Papers, vol. 62, no. 8, pp. 2013 – 2023, August 2015.
C. Weltin-Wu, G. Zhao, I. Galton, “A Highly Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid State Circuits Conference, 2015, Digest of Technical Papers, February 2015.
C. Venerus, I. Galton, “A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With A 2.8-3.5 GHz DCO,” IEEE Journal of Solid State Circuits, vol. 50, no. 2, February 2015.
C. Venerus, “Delta-Sigma FDC Based Fractional-N PLLs with Multi-Rate Quantizing Dynamic Element Matching,” Ph.D. Dissertation, University of California, San Diego, 2013.
E. Familier, C. Venerus, I. Galton, “A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones,” IEEE Transactions on Signal Processing, vol. 61, no. 17, pp. 4270 – 4238, September 2013.
E. Familier, I. Galton, “A Fundamental Limitation of DC-Free Quantization Noise With Respect to Nonlinearity-Induced Spurious Tones,” IEEE Transactions on Signal Processing, vol. 61, no. 16, pp. 4172 – 4180, August 2013.
C. Venerus, I. Galton, “Delta-Sigma FDC Based Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 1274-1285, May 2013.
N. Rakuljic, I. Galton, “Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 593-602, March 2013.
G. Taylor, I. Galton, “A Reconfigurable Mostly-Digital Delta-Sigma ADC with a Worst-case FOM of 160dB,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 983 – 995, February 2013.

 

 
RF and Analog Engineer
Author brief is empty
1 Comment
  1. KimJ 2 years ago
    0
    -0

    Good!

    5

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2021  ValPont.com

Forgot your details?