Low Power Design In Algorithm Level

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Low Power Design In Algorithm Level

In this slides, we talk about some power techniques at algorithm level. Topics touched include

  1. different binary data representations and their LP effects in transmission and processing
  2. Data bus and address bus low power
  3. Gray coding and LP
  4. Optimized FSM encoding for LP
  5. Algorithm transform for LP
  6. Operation reduction for LP
  7. Operation order change for LP
  8. Hardware sharing for LP


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Highlights: 81 words, 1 images, 1 docs
We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.

1 Comment
  1. chriszhou 4 years ago

    Good touch on some algorithm level low power design techniques. I’d say most are actually not used in practical RTL design since their power saving is very trivial compared to overall system pwr consumption and the techniques introduce difficulty to design and maintain.


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