Learn Nand Flash and Verilog Simulation Model from Nand BFM Model

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Learn Nand Flash and Verilog Simulation Model from Nand BFM Model

I am working on an FPGA project which uses nand flash controller to drive an external flash memory. This is my first touch on nand flash. Reading flash memory datasheet is very helpful to understand how it works.

micron_nand1

But I found since I have flash controller IP in FPGA, I can set up a simulation environment to verify the whole process and get a better understanding of how flash memory works. The design is straightforward:  an arm processor runs inside FPGA which talks to arm AHB bus. The latter talks to flash controller. Note I am not using Xilinx flash controller and I am using an RTL IP. Nand flash controller then talks to an external nand flash memory which is from Micron. Micron provides BFM simulation model for its flash memories. For example, you can find one of the lasted models in:

http://www.micron.com/parts/nand-flash/mass-storage/mt29f64g08ajabawp

 

In the following, I just use an old one to show the concept and this file is also simplified to just show the concept. Note this simulation model is well written. It not only helps me to understand how nand flash works but also shows me how to write a good Verilog behavioral model.

1. It first defines IO ports and timing parameters. For IO ports, you can check with following table for their functionalities.

micron_nand2
If your nand flash controller is RTL without timing in sim, these timing parameters are not important since the driver side is untimed. But it still works. If you run post-par sim with timing back-annotated netlist, these timing parameters are important to verify the interface timing.

2. It then defines mem_array as:

This array models flash memory cells. This is normally the first thing you want to monitor and check to see for example if data is properly written into flash.

3. It then defines an initial block. Here it uses $readmemh to initialize mem_array.

4. It then defines several Verilog tasks, cmnd_reset, clear_data_register, clear_cache_register, load_register, erase_block, and program_page. For example program_page shows how data is moved from data_reg or cache_reg to mem_array.

5. It then defines several always block, address_latch, command_latch, data input, and data output. Command latch is important because it also does command decoding and execution. For example

this codes says with input data as 15h, if previous input data is 80h and row is valid, call program_page task to program page with 1’b0. If last input data is 80h but row is not valid, clear 80h status. Otherwise do nothing. This is how flash memory decodes a sequence of input data to detect proper command.

In data output always block, please note how the model generates output with random timing:

6. note throughout the file, you can see something like

or

This is what a good model normally does – print the module beh and status to sim log file. It has option to be turned off by user to simplify the log file.

The simplified model is as below:

 

 

 
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