LBIST and MBIST

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LBIST and MBIST

DFT normally consists of LBIST, MBIST, and some supporting logic. LBIST is to test combinational and flip-flops based on scan chain. MBIST is to test embedded memory.

 

A chip can include multiple digital cores. Each core includes one LBIST logic. Each core can have multiple clock domains. Each clock domain has one OCC block, on-chip test clock generator, to control shift and capture clock for that clock domain in test mode. OCC basically muxes functional clock, CLK1 and CLK0 in diagram, with shift clock. Shift clock comes from SCLK_Ctrl block, shift clock controller. For details of OCC, check A Guide to DFT Test Clock and On-Chip Test Clock Generation (OCC). SCLK_Ctrl is per core and it selects which clock drives shift clock. Shift clock could come from TCK or some other clocks on chip.

Scan chain configuration is flexible. Most likely one scan chain consists of flip-flops belonging to one clock domain. It is also possible one scan chain contains multiple segments with each segment for one clock domain.

There could be tens of or hundreds of scan chains in one core. Scan chains can be driven by on-chip LBIST or off-chip test equipment. One core has only one on-chip LBIST. It has PRPG to generate vector ad MISR to check result. A “Scan Chain Router” sits between LBIST controller and scan chains. This router can stitch multiple scan chains together. It is particularly important in case of using off-chip test equipment to do ATPG test. Due to limit availability of pads for test, number of “multi-chain ports” for off-chip ATPG test is normally much less than number of scan chains.

 

 

One chip has only one TAP controller which interfaces to JTAG ports on one side. On the other side TAP controller drives LBIST and MBIST blocks in multiple digital cores. Although there is only one LBIST per core, there can be multiple MBISTs in one core. DFT tool groups embedded memories in one core into several memory groups mainly based on memory clock domain and physical location. Memory grouping also takes test time, power, etc. into consideration. Then one MBIST is generated for each memory group. For memories in one group, MBIST can test them in parallel or in serial.

 

 

Here is a good article about LBIST.

 

LogicVision is a popular DFT tool. Here is a good slides.

 

 

 
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