My other post, Split-nwell and Merged-nwell Cells and Their Usage in Low Power SoC, talks about split-nwell and merged nwell cells used in low power SoC design. A concern with merged nwell cell is the possible latchup issue.
There are ample materials about CMOS latchup issue online. A latchup is the activation of parasitic bipolar devices in a CMOS logic which results in a low impedance path from the power to ground. This short causes high current which causes temporal malfunction or even permanent damage to the CMOS cell.
As shown in below, the parasitic bipolar structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other.
Redraw the schematic as below.
During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it. A common cause of latch-up is a positive or negative voltage spike on an input or output pin of a digital chip that exceeds the rail voltage by more than a diode drop. Another cause is the supply voltage exceeding the absolute maximum rating.
But as mentioned in my other post, merged nwell cell has its nwell and PMOS VDD connected to different supplies. So equivalent circuit is like below. The issue is if nwell supply V_nwell is less than PMOS VDD, latchup can happen.
When V_nwell is low, PNP is first turned on and current (A) flows from PNP’s drain to source. This current makes NPN’s gate voltage high which further turns on NPN and allow current to flow from NPN’s gate to source. Therefore a low impedance path is formed from VDD to ground.
So SoC power planning needs to make sure V-nwell is not less than VDD. A lot of times they come from the same power source and it is just VDD is switched or gated version of V_nwell. Is it good this way? We need to check IR drop. IR drop consists of dynamic IR drop and static IR drop. For dynamic IR drop, if V_nwell sees more current flowing or more impedance on power distribution network, V-nwell may be smaller than VDD and it can cause latchup. But dynamic IR drop normally lasts for a short period of time, latchup will be stopped once dynamic IR drop is gone. Static IR drop is more of a concern. If static IR drop causes V_nwell to be lower than VDD for a long time, we will see high leakage and the cell likely malfunction too.
As a matter of fact, I am a backend guy. I am not sure
- latchup will be stopped when dynamic IR drop is gone
- how low V_nwell less than VDD will trigger latchup. I assume a small delta should be ok.
A CMOS circuit expert should have a better idea.
BTW, here is a good short intro about CMOS latchup.