Here are some questions I have for latch related design
- Why does clock gating ICG cell uses latch and not flip flop?
- Do we need to close timing on latch?
- When do we prefer to use latch rather than flip fop?
Fortunately there are materials online talking about latch. About question #1, there is quora link Why is the ICG cell latch used instead of flip flop? Is the latch level triggered?. In summary,
- A FF is typically made up of two latches – one low-sensitive and one high-sensitive. Therefore, you’ve doubled the area of the “Memory” element in the ICG.
- Swapping the latch to the FF has also increased the power consumption of the ICG
- By far the most important: Now the enable input is captured on the falling edge of the clock in the previous cycle. Therefore, whatever logic is generating it has to do so within half a clock cycle. Using a latch, the logic was able to take the whole clock cycle (minus the setup time) to calculate the enable (because “next cycle’s enable” is allowed to change all the way up to the rising clock edge), but now it’s only got half a clock cycle.
So, by swapping the latch for a FF, you’ve increased area, increased power consumption, and made the timing much harder to meet. Not good.
I am not a big fan of area and power saving. ICG area and power is such a small portion of the whole chip. A little bit saving here is by no means noticeable. The relax on clock enable signal timing to a full cycle is an interesting point. But the clock enable is generated by FF driven by “clk in”. Half a cycle should not be a big deal to meet timing since there is no combinational logic in between. If it is a big deal, it is hard to imagine how we close timing with complicated combinational logic on data path.
So as you can see, I am not convinced latch is a better choice than a FF for ICG.
Above timing relax argument introduces another topic which is how we deal with timing closure of a latch. I have been told before STA does not check timing on a latch or in other words latch is transparent at STA timing closure. This sounds not right. Googled this topic and bumped into this article, Latches & Timing. It analyzes below circuit that between two FFs there is a latch whose enable is driven by inverted clock.
While doing STA, Timing reports will be generated according to Case A and Case B. In reality, the timing when the latch is enabled is the same as if the latch were simply a transparent delay element (Figure 5.)
The least preferred, most accurate and the best way to judge the timing of latches (once it is made sure that latch will be transparent while timing this path) is to make the latch transparent by putting a case analysis on the enable pin of the latch. After this, the EDA tool will be able to time the two segments as one complete path. The reason we prefer this least is that the latch may not always be transparent while timing path 1 in the best-case condition where time borrowing is not needed. And the tool will miss all the paths which do not require time borrowing and hold time check at the latch endpoint.
The article seems to agree that we do not need to check timing on latch and we can treat latch as a transparent device with some delay in STA. But this does not sound right. Find a video on youtube
This one is more of what I am looking for. It says latch has setup and hold requirement just as a flip flop. Latch’s setup/hold is relative to the deassertion of latch’s EN input.
Let me use above latch based ICG as an example. Let’s say we don’t care about latch timing at all. Let’s assume enable signal is deasserted before clk_in’s rising edge. (This is actually hold violation of latch timing since clkin’s rising edge is the deassertion of latch’s EN signal). Latch sees Enable go low and it makes its output low too but with a small delay. This delay can cause output clock glitch.
So I think latch’s timing needs to be checked and satisfied.
Latches & Timing has an interesting statement of usage of latch.
Latch-based designs have small die size and are more successful in high-speed designs where clock frequency is in GHz. In flipflop-based high speed designs, maintaining clock skew is a big problem, but latches ease this problem. Hence use of flipflops can limit the design performance, in cases where the frequency of the design is limited by the slowest path. Also when process variation is considered, latch-based design is dramatically more variation-tolerant, resulting in a better yield and/or allowing a more aggressive clocking than the equivalent design with flipflops.
So latch finds its way in high speed digital design? It does not sound right either since to my knowledge flip flop based design still dominates.
If you have some thought about this topic, please feel free to leave your comments.