Is Violation of Retention Flip-Flop Clock Parking a Real Issue

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Is Violation of Retention Flip-Flop Clock Parking a Real Issue

 

There are two types of retention flip-flops, retFF with retention control pin and retFF without retention control pin.

Below is retFF with retention control pin, PD. When PD is 1, retFF is in retention mode when the master latch 210 can be powered down and the slave latc 240 needs to stay powered to keep the value.

Below is another type of retFF with retention control pin, RETAIN#. When RETAIN# is low, retFF is in retention mode.

Note RETAIN# is only used to AND-INV with CLK. If we change the circuit a little bit to AND RETAIN# with CLK and move this AND gate out of retFF, we can get below circuit. What is inside the blue box is really a retFF without retention control.

Two things worth mentioning about this AND gate.

  • First, this AND gate needs to be in always on domain (AON). The CLK input to this AND gate is in gate-off power domain. It is intuitive to insert an isolation cell between CLK and this AND gate. As a matter of fact, it is not necessary. This AND gate itself should be the isolation. To be accurate, this AND gate is an iso to low cell with retention control signal, RETAIN#, as the isolation control signal of this iso cell.
  • Second, this AND gate or isolation cell is inserted during backend process. These days BE low power tool can easily take care of this task to avoid the burden to instantiate AND/iso gate in RTL.

 

So the AND gate is also an isolate low cell which means this retention-control-less retFF is a clock park low type. (Note clock park high type retention-control-less retFF also exists) To make retention work, the following retention entry sequence should be followed.

  1. Assert clock gating to gate off all the clocks and clocks should be parked at low state.
  2. Assert retention control, RETAIN#
  3. Remove main power but keep AON power on. RetFF is in retention mode and value is kept.

Retention exit sequence is just the opposite.

  1. Apply main power back
  2. Deassert retention control, RETAIN#
  3. Deassert clock gating

 

As can be seen, above sequence requires clock to be parked low for this clock-park-low type retFF. The question this article is going to discuss is if there is an issue and under what condition there is an issue if clock is parked high.

 

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