Introduction of PTPX Power Analysis Flow

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Introduction of PTPX Power Analysis Flow

There are lots of online materials introducing Synopsys ptpx flow. This short article just captures the fundamental commands to illustrate how ptpx works. It serves as a quick reference to designers.

Below is the typical ptpx flow. First we need to run gate level simulation with SDF timing annotated. Let simulator dump out waveform which serves as switching activity file during ptpx. Ptpx will read in design from netlist, switching activity from the dumped waveform, parasitic such as cell and interconnect capacitance from SPEF, and standard cell and hard micro libraries. Armed with these four inputs, Ptpx is then able to report average power of your design during the waveform specified. Note ptpx does not report power profile. So it is important to select the waveform wisely. Waveform window should not be too long to shorten ptpx run time and should not be too short which may not represent the state we want to check power. For some lessons learned and tricks, I have another post, About power analysis using ptpx .

Assume there is a design with top module called decoder. Decoder.vg is the netlist of this design and it resides in /netlist folder.

Below commands are in tcl and should be run the root folder.

First read in netlist

Note if the design has hardmacros, hardmacro netlist also need to be read in. Assume decoder consists of one memory hardmacro, ram256x32. We should do

Then do

Read in SPEF file

Also read in SPEF of ram hardmarco

Read in timing constraints. Assume timing constraint sdc file is in /timing folder.

Prepare some ptpx variables

Read in waveform vcd file

Pay attention to “-strip_path”. We need ptpx to understand where is decoder module in simulation hierarchy. Here we assume there is a top test module called “test_wrapper” which instantiates decoder directly.

Finally, let ptpx to report power

Ptpx report is straightforward as below. But as can be seen, there is one drawback. Report just recursively reports power of each module/cell/hardmacro. But netlist normally has tons of std cells like buffers, inverters that are inserted during synthesis, PnR, and timing closure. With them in rpt file, it is hard to see how the design submodules consume power. Therefore normally we need to post process the report and extract only decoder, u_decoder_fsm, and u_decoder_datapath power numbers.

Hierarchy Int_Pwr Switch_Pwr Leakage Total %
——————————————————————————–
decoder 2e-03 3e-03 4e-04 5e-03 100.0
u_buf1 0.000 0.000 1.2e-11 1.2e-11 0.0
u_buf2 0.000 0.000 4.2e-11 4.2e-11 0.0

u_decoder_fsm

u_fsm_buf1 0.000 0.000 1.2e-11 1.2e-11 0.0

….

u_decoder_datapath

u_dp_buf1 0.000 0.000 1.2e-11 1.2e-11 0.0

….

Ptpx can also be configured to report power of specific power domains and specific cell types.

 
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