[Interview] ASIC/FPGA Engineer Basic INTVW Questions

Make it to the Right and Larger Audience


[Interview] ASIC/FPGA Engineer Basic INTVW Questions


Here are several questions I met before when I interviewed an ASIC engineer position before.


1. Draw a divide by 2 circuit.

[hint] Connect d-FF’s q-bar (invert of q) to d pin.


2. Draw a divide by 3 circuit. Uses positive clk edge and duty cycle is 33%.

[hint] It was asked to state machine method. Draw the waveform and show state transits from 00, to 01, 10, and then back to 00. Then based on state transition table, design the connection around 2 FFs (since 2-bit states).


3. Draw a divide by 3 circuit but duty cycle is 50%.

[hint] Using above circuit, delay its output by half clk cycle (using FF with neg clk edge), then OR with original output.


4. Can circuit outputs in 2 and 3 be used as clk directly?

[hint]¬†No.¬†The output is comb logic output so it is glitchy and can’t be used¬†as clk directly. Need to add one more FF,¬†with d¬†pin connected to¬†circuit output and clk pin connected to original fast clk. Then this d FF’s q¬†can be used as clk.


5. Single sequence detector.

[hint] this is a typical sequence (like detecting 0110) detect question. You can find answer in lots of books. Need to be familiar with FSM design.


6. What is delta delay issue and why it is important in RTL sim and zero-delay gate sim?

[hint] In¬†VHDL and Verilog, assignment¬†normally introduces delta delay. For example, if you have a clk divider or clk gating cell, its output is delta delayed from original clk. If data goes thru a FF,¬†the output¬†(edge) is also delta delayed from clk edge. So, for example,¬†if you have cascaded clk gating cells, final clk can’t capture¬†data generated from original clk correctly since¬†clk¬†edge occurs several delta delays after the data edge.¬†A common¬†way to fix the issue¬†is make sure¬†generated clk¬†has no delta delay from original clk.


7. Design an async FIFO and also if read and/or write are bursty how to calculate the FIFO depth.

[hint] Typical FIFO question. You can find answers in books.


8.¬†How UART and I2C works. Uart doesn’t have clk, how to capture the data?

[hint] You can find UART RTL in opencores.com. Basically use over-sampling to capture data.


Good Luck!

Profile Photo
Senior Engineer
Author brief is empty

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.


©2021  ValPont.com

Forgot your details?