HW Mailbox for On-Chip and Off-Chip Inter-Processor Communication

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HW Mailbox for On-Chip and Off-Chip Inter-Processor Communication

It is common for modern ASIC to have multiple processors on chip. Mailbox is one way to support inter-processor communication. Mailbox can also be used for communication between processors on different chips. An interesting blog can be found at INTERPROCESSOR COMMUNICATION: Raspberry Pi 2 ARM-GPU IPC.  It employs mailbox mechanism as below:

This drawing is simplified and the blog does mention how interrupt is used with mailbox.


Below is a generic mailbox structure.

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