As mentioned in our other post, Is Violation of Retention Flip-Flop Clock Parking a Real Issue, clock parked low is normally a requirement for retention flip flops for them to retain value properly during power down sleep. Here is a typical implementation of retention FF. Note the “AND” gate is NOT inside retention FF. As a matter of fact, this “AND” gate is actually a power isolation low cell and RETAIN# is active low iso enable signal. The “CLK” signal, input to AND/isolow cell, is required to be parked low before sleep or before RETAIN# is asserted low.

Let’s take a look of a very simple scenario. There is a clock source at chip top level. Its clk output is wired to core0 and core1. Inside core0 we add a ICG cell, clock gating cell, to gate off clock before sleep.

A typical ICG cell works as below.

But using this ICG cell in above simple use case does NOT work. Next we will discuss why and several ways to resolve it.

 

Precise-Design

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