Third parties normally deliver their designs in hard macros for IP protection. In most cases Verilog/vhdl version is also available but IP acquirer needs to pay more, if not much more. For FPGA design, the popular format to deliver hard macro IP is EDIF. Sometimes for Xilinx fpga design NGC format is also used.
First let’s talk about implementation. If you use Xilinx XST for synthesis, in ISE, you can add your top level and sub module Verilog files, Xilinx xco files for XCO cores, and Xilinx xaw files for XAW cores. No need to add EDIF files but they need to be copied into ISE project directory. Then when you run XST in ISE, you will get XST:766 warning saying a blackbox is generated for components. This warning can be ignored for eg, CORE Generator modules, instantiated EDIF files, and instantiated primitives. To avoid blackbox warning, you can do:
In VHDL file
attribute box_type : string;
attribute box_type of <component_name>: component is “black_box”;
In Verilog file
//synthesis attribute box_type <component_name “black_box”
XST generates synthesized EDIF netlist. Then ISE goes into translate phase where NGDbuild is called to stitch all NGO files together into NGD file. If read in netlist is in EDIF, edf2ngd is called to convert edf to ngo. If read in design is in NGC, ngcbuild is called to convert ngc into ngo. Then NGDbuild will merge all NGO files into NGD. During this process, NGDbuild will find the missing modules/EDIFs in the project dir. If EDIF files are in different directories, you can run NGDbuild with -sd to specify path to dir that contains EDIF files.
A popular synthesis tool in FPGA design is Synplify Pro, which delivers better results and shortened run time than XST. To use Synplify, you need to create a project file and then add designs to it.
For EDIF files:
add_file -edif *.edf
For vhdl files:
add_file -vhdl -lib work *.vhd
For sdc constraints:
add_file -constraint *.sdc
For XCO core with ngc files:
add_file -Xilinx *.ngc
For XAW core with vhd files:
add_file -vhdl -lib work *.vhd
Once you add all the files, you need to specify which module is the top level design. You can use imp options, VHDL, top level entity to specify it. Note XCO core can also be in EDIF format, in this case, add it like an EDIF core. You can write constraints in sdc directly. If you are more comfortable with Xilinx UCF, you can write constraints in UCF and then use
ucf2sdc -osdc out.sdc -iucf in1.ucf in2.ucf
to convert UCF files into sdc. For Synplify synthesis, it takes in clock and pin location constraints. Pin location information is kept in generated EDIF netlist so later you can use EDIF and ucf in ISE to do implementation. Synplify outputs are EDIF netlist so ISE will take in this EDIF file and convert it to NGD file and start PAR process.
EDIF files can’t be used for simulation directly. Xilinx provides edif2vhdl tool to generate behavioral model vhdl files for sim from IP core’s EDIF file. Edif2vhdl first calls ngdbuild to convert edif to ngd and then calls ngd2vhdl or netgen to convert ngd to vhdl. NGDbuild produces a netlist composed of NGD primitives (Xilinx specific). So after NGDbuild, simulation needs to use SimPrim library rather than UniSim library
If you use Synplify, it can generate vhm files out of EDIF. Vhm can be used in simulation like a vhdl file.