How to Handle Power and Isolation in Softmacro, Hardmacro, and Firmmacro

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How to Handle Power and Isolation in Softmacro, Hardmacro, and Firmmacro

Here we talk about how to handle softmacro, hardmarco, and firmmacro in terms of power related tasks. Discussion covers below topics.

  1. how macro specifies its power pin information
  2. how macro specifies its boundary pins are in which power domain
  3. how top module makes power connection to macro
  4. how top module adds and checks isolation to macro

Above are discussed not only in term of backend process flow but also from upf simulation point of view. These two ideally should match each other. Backend process represents what the silicon looks like. Upf sim needs to match so that it simulates the real case. Later we show an interesting issue how these two can mismatch.

 

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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.
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