How to Debug Issue Due to Glitchy Clock

Make it to the Right and Larger Audience


How to Debug Issue Due to Glitchy Clock

If a D flip-flop clock is glitchy, what does the output become? If we look at RTL simulation waveform we can see output behaves just like under a normal clock edge. This is because if DFF is implied by rtl code, clock pulse width is not checked in simulation. If DFF cell is instantiated the DFF model does not flag clock glitch.

If we look at SDF back annotated gate level simulation waveform, we can see output becomes X. This is because D flip-flop model in timing GLS checks clock pulse width against real DFF timing requirement and if violation is found DFF output is driven to X. But does it really reflect what happens on silicon? In reality FF output can be unknown but is there still some “predictable” behavior to help debug glitchy clock issue?

We will show under what condition DFF output does not become unknown and how to debug when it does.

The analysis result is based on how DFF is implemented. In this post, we assume below DFF architecture. This master-slave type DFF is widely used in today’s deep submicron processes.

First let’s see how this DFF works.

When clock is low, T1/T4 are closed and T2/T3 are open. So node A and B inside DFF are already updated with outside data change. This is counter intuitive. Lots of designers assume when clock=0 DFF internal state is not changed. This is not true for this master-slave type DFF.

When clock is high, T1/T4 are open and T2/T3 are closed. DFF is isolated from D input. Master inverter loop holds data.

Now let’s see glitchy clock impact but under the condition that D input is stable. Below diagram shows DFF states when D input is stable at 0 or 1. In this case a short pulse on clock won’t change anything, no node is going to toggle. So glitchy clock does not affect FF with stable D input.

What if D input toggle when clock is glitchy? Let’s check D toggles from 0 to 1 first. When clk=0, Master latch node A and B changes to match D. Then clock goes high, slave tries to discharge to node B. But clock is glitchy so clock goes back to 0 again. This discharge may be enough to make slave toggle to 0 or not enough to make slave stay at 1. Note since clock goes back to 0 after glitch, T4 is closed so slave has an active comb logic loop and it will quickly end up at 0 or 1.

The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 359 words, 2 images
Electrical Engineer
Author brief is empty



Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.



Forgot your details?