Yeah, it is a weird a question but it is the question we got from our client recently. Customer is always right. So let’s see how it pans out.
What they are asking is, for example, if an external component asserts an input pad for 1ps, can this chip capture this event? No? How about 1ns? Still no? Then how wide should the pulse be for the chip to capture it?
The path from input pad to the possible capture logic is shown. Signal coming in first meets PAD logic. Inside chip we may have deglitch circuit to smooth out possible glitches at pad output. Deglitch circuit is likely an analog design and doesn’t need a clock. Deglitch circuit can be enabled or bypassed.
Then input signal can see various logic depending on the functionalities. Here are just four examples.
- oversampling circuit is one way to capture input signal state. Oversampling is commonly seen in an UART design.
- Synchronous circuit is quite straightforward but it has the risk of missing narrow pulse.
- Dlatch can be used to capture input’s rising or falling edge so it won’t miss narrow pulse but it needs to be cleared before it can capture the next edge.
- ARM GPIO module is commonly used in ARM based SoC design. It allows firmware to configure a pad to be input or output. If output, fw can drive output value. If input, fw can read back current pad status. This GPIO module also has the capability to generate GPIO interrupt to arm processor. Interrupt can be configured to be level or edge. If level, input is directly hooked to interrupt output. If edge, input is delayed using GPIO module clock and uses delayed version to detect rising or falling edge.
Let’s see at each stage how wide a pulse can pass.
PAD is actually a complicated design. Simplified diagram is below.
Here is a more complicated diagram with ESD protections. Note ESD protection is one of Pad’s critical features.
Even above is far from full. For example, a pad needs to have controls to set output driving strength and slew rate on the output side. On the input side, it may have hold capability which means even outside driver is removed the pad can hold its value. It may also have input hysteresis control which helps to smooth out a narrow pulse.
Pad datasheet specifies input delay at various PVT conditions. It highly depends on process node and pad design. In general, input delay is about 1-2ns for a generic GPIO pad.
As mentioned, deglitch circuit is analog based. Here we assume it is disabled.
For synchronizer, input needs to at least one clock cycle plus a FF setup/hold time long to be able to pass through synchronizer and be seen by downstream logic. Assume synchronzier clock is 100Mhz, input needs to be least 10ns long. FF setup and hold sum can be just 0.2-0.5ns. So total is 10.2-10.5ns.
For Dlatch, input is connected to its clock to capture rising or falling edge. Need to check Dlatch clock min pulse requirement. it is normally <1ns.
For ARM GPIO module, edge detection actually uses synchronizer. So result is the same that if GPIO module is driven by 100Mhz clock, input needs to be at least 10.2-10.5ns.