High Leakage when Retention FF is in Low Power Mode but not in Retention

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High Leakage when Retention FF is in Low Power Mode but not in Retention

Retention flip-flop is widely used in low power soc design. During low power mode, aka power down sleep, retention flip-flop can be cut out of the main supply to save power while use always-on supply to retain the value. Below is a typical retention FF schematic. It consists of a master latch and a slave latch. Master latch is powered by main supply which is shut down during low power mode. Slave latch is powered by always-on supply which is kept high to retain value.

During low power mode, the retention control signal, RETAIN_b, needs to be low. If it is high, not only retention FF value is lost but also there could be a high leakage on always-on supply. In this article, we will discuss how this leakage occurs and how to resolve it. An important notice is low power mode is not just power down sleep mode but also includes module reset state. In module reset state, chip always-on supply is high while module’s main supply is cut off to save power. High leakage could also happen in this scenario just like in power down sleep case.


Next let’s draw below highlighted section in more detail.


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We are a small design team with many years of experience in ASIC/FPGA IP and system designs which involve UART, SPI, AHB, AXI, ACE, USB, PCIE, etc.


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