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Your most weird board design issue

Your most weird board design issue
2 Voices |2 Posts |300+ | Discussion Rooom: PCB and Board Design

This topic contains 1 reply, has 2 voices, and was last updated by  BarryHampe 5 years, 3 months ago.

  • Author
  • StanH
    Senior Staff Engineer

    Hi Guys

    It is interesting to share our most weird board design issues.

  • BarryHampe
    Senior Electrical Engineer

    Stan, I re-post it here:

    In summary, two lessons learned recently:
    1. pay attention to pwr trace sharing
    2. protect power of sensitive modules such as PLL

    We are in the low power wearable industry. For the micro-controller we are using, some of its functions works most of the time but occasionally it fails. At the beginning, the pattern it fails seems totally random. After a painful debugging, we realize why. The function fails because the clock it gets varies, which in turn is due to PLL gets noise on its power supply. PLL’s power trace is shard with main digital power. When some other function is running (not all the time), it draws lots of current. Since pwr trace is shared, IR drop or may be Ldi/dt causes noise on PLL power. Issue is confirmed when we ran a clean power to PLL.

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