MCU and DSP

Western Digital proposes #OmniXtend to #RISC-V

as a open-sourced cache coherent interconnect fabric

#Open-ISA VGEA board for smart-lock

Keynote, design thr next billion chips, how #risc-v is revolutionizing thd hardware

From sifive cofounder and cto

#risc-v #ai chip startup Esperanto raised 58Million for 7nm AI chip

Esperanto Technologies raises $58 million for 7-nanometer AI chips |…

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#risc-v chip designed and manufactured in India

Risc-v foundation news. researchers at Indian Institute of Technology, Madras (IIT-M) have designed and booted up India’s first microprocessor dubbed “Shakti” (meaning power), which is targeted at mobile computing and other devic…[Read more]

Microsemi releases #risc-v based low power fpga system for linuc plus real time app

Worlds first RISC-V-based FPGA SoC runs Linux

http://linuxgizmos.com/worlds-first-risc-v-based-fpga-soc-runs-linux/

Microchips Microsemi unit unveiled a low power,…

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#huawei releases #arm based server processor chip

It said its latest 7 nanometre, 64-core central processing unit (CPU) would provide much higher computing performance for data centers and slash power consumption. It is based on the architecture of British chip design firm ARM – owned by…[Read more]

#cortex-m interrupt not serviced

debugged an interesting issue recently. interrupt to cm3 is asserted high but cm3 doesnot service it. finally realize cm3 is configured to treat irq as pulse type and not level type. below is from arm doc.

The processor supports both level and pulse…[Read more]