ASIC and FPGA

[JingZh Staff Engineer]

I see BE team inserts filler cells here and there. Wondering what it is and why use it in BE process?

[UManish Staff Engineer]

Fill cell is to complete the standard cell rows by making continuous M1 VDD/VSS supply rails. Cell utilization is normally less than 100%, so they will be void (no stand cells) in standard cell rows but we need to make VDD/VSS rails continuous so need to insert fill cell. Fill cell also completes the cell to cell abutment for other layers like nwell and implant.

Other than fill cell, you can also use decap cell for this purpose. However, since decap cells may use thin gate oxide gate to max the cap value, their leakage could be high. Fill cell doesn’t have cap but it has latch protection. You can check with lib team for details.

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