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Verilog test BFM to drive and monitor internal AHB bus

Resolved Verilog test BFM to drive and monitor internal AHB bus
2 Voices |3 Posts |1000+ | Discussion Rooom: ASIC and FPGA

This topic contains 2 replies, has 2 voices, and was last updated by  earnestwu 4 years, 4 months ago.

  • Author
    Posts
  • earnestwu
    Senior Engineer
    TI

    We have a design with an embedded arm processor. We can do software-hardware co-sim and run simple c test code on arm processor. But we’d like to have another way which we can bypass (sort of disconnect) arm processor and use a TB BFM to drive AHB bus. Note we don’t want to touch rtl code. Is it doable?

  • In Verilog, you can specify signal hierarchy path to drive or monitor DUT internal signals. For example:

    Note above uses force to override RTL drives. You may see someone uses

    to replace the forcing. Above assignment does not work since it causes multi-driver issue.

     

  • earnestwu
    Senior Engineer
    TI

    I see. Thanks.

    Normally force/release are used as a pair. I don’t see release is used in above so test bench drives the internal signal all the time. I think it is good.

    Along the line of using assignment, I think we can use ifdef in RTL. Idea is if a string is defined, internal RTL connection is disconnected by ifdef. But it adds some change to RTL.

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