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Stitch two scan chains of different clock domains make timing closure worse?

Stitch two scan chains of different clock domains make timing closure worse?
1 Voices |1 Posts |300+ | Discussion Rooom: ASIC and FPGA

This topic contains 0 replies, has 1 voice, and was last updated by  Ravenhill 1 year, 7 months ago.

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  • Sarkar has a good post of at speed test. http://www.valpont.com/basics-of-at-speed-dft-test/pst/

    One of its example stitches two scan chains of different clock domains together. I heard it complicated timing closure. How so? At speed is done at each chain separately. Shift clock is slow so no issue?

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