ASIC and FPGA

Make it to the Right and Larger Audience

RTL Simulation Fails due to Clock Gating Delta Delay

Resolved RTL Simulation Fails due to Clock Gating Delta Delay
3 Voices |4 Posts |1000+ | Discussion Rooom: ASIC and FPGA

This topic contains 3 replies, has 3 voices, and was last updated by Profile Photo SD-RTL-DGN 4 years, 9 months ago.

  • Author
    Posts
  • KLiang
    Engineer

    My RTL simulation is failing. Symptom is some FF does not delay data but passes data directly through. Turns out clock toggles at exactly the same time as the data. This is because the clock of latching FF is not the clock of the launching FF, FF that generates the data. Latching FF uses gated clock but due to gating logic there is a delta delay between gated clock and original clock. Data is generated from original clock so data has one delta delay from original clock edge too. As a result, using gated clock to latch data generated from original clock causes this issue.

    But my question is how to fix it since VHDL and Verilog assignment always causes delta delay. I can put in some delay in RTL to pass simulation but RTL doesn’t look good. Hope there is other way to fix it.

     

  • JingZh
    Staff Engineer

    Kliang, how about you also add delta delay to the clock of the launching FF? So launching FF clock is one delta delayed version of the original clock so its clock edge is perfectly aligned with latching FF clock edge. In other words, all FF’s clocks have the same delta delay.

    • KLiang
      Engineer

      Thought about this way too. It is ok for my relatively simple design. But I am thinking for a complicated design, there may be lots of clocks and there may be several layers of clock gating. It is not easy to align all the clocks. For example, you add one clock gating, you may need to add one more delta delay to all the other clocks?

  • Good question. Believe it or not, even in large companies, sometimes this issue pops up and not all engineers have a good handling of it. Yes, there is a better way to handle it. You should remove the delta delay due to gating logic. In this way, no matter how many layers of clock gating you add, all the clocks are aligned (to the original clock). To do this, don’t use Verilog or VHDL assignment to do clock gating. Instead, instantiate a library cell and set library cell to be zero delta delay.

You must be logged in to reply to this topic.

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

Sending

©2020  ValPont.com

Forgot your details?