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Ring Oscillator in FPGA?

Ring Oscillator in FPGA?
2 Voices |2 Posts |300+ | Discussion Rooom: ASIC and FPGA

This topic contains 1 reply, has 2 voices, and was last updated by  Precise-Design 4 years, 9 months ago.

  • Author
    Posts
  • earnestwu
    Senior Engineer
    TI

    endif
    wire osc1, osc2;

    nand #1 na1 (osc, nrst, osc2);
    not #1 n1 (osc1, osc);
    not #1 n2 (osc2, osc1);

    endmodule

     

    Got above code. It is claimed that it oscillates and outputs some clock in FPGA. Basically it is a ring oscillator which contains a comb logic loop. Does anyone know if it works in FPGA? It may be good to generate some clock handy.

     

  • Precise-Design
    Post count: 1

    Ring oscillator is commonly used in ASIC for PVT monitoring and even for DPLL oscillator. It does find some use cases in FPGA too. One of them is to generate a unique code for an FPGA chip for security reason. You can find some details here:

    http://trudevice.com/Workshop/program/18%20L.%20Feiten%20TRUDEVICE_2013.pdf

    So I’d say yes we can use RO in FPGA. But your code may not be good enough. It only has three delay cells for RO, one nand and two not. So the oscillated clock freq may vary quite a bit from chip to chip. In asic, one RO may have hundreds of delay cells and there is a control to select how many of them are active (so others are bypassed). In this way, we can use another accurate clock such as xtal to detect RO freq and then use this control to adjust RO freq. Even so RO is simulated across chip PVT before TO. You can omit this and do trial and error in FPGA. Still you better have some way to adjust RO active delay cells and therefore adjust RO freq.

    Of course you need to make sure FPGA synthesis tool doesn’t optimize this RO out by combing delay cells. Also clock constraint is needed for digital circuits that divide RO out down.

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