ASIC and FPGA

[BoxinKuo Engineer I Post count: 2]

I have a design with two FPGAs. One interfaces to the outside word (via ADC) and also does some pre-processing. The other FPGA does post-processing. Need to move large amount of data between the two FPGAs. Do I need SDRAM to buffer data?

[StanH Senior Staff Engineer]

It depends. Data transfer rate can be very high since it is FPGA to FPGA and you can always use many data signals to achieve higher data rate. So likely you can dump data from one FPGA to the other without external buffer. (of course you need to consider data assemble and de-assemble overhead)

But if your design needs to realign data or add some other information like data header/footer/etc, you may need to buffer data externally assuming internal SRAM is not large enough. SDRAM can be a good candidate for external buffer due to its mem size and speed. However, SDRAM is not that straightforward. It has many states and overheads like refresh, activation, read, write. You need to calculate if SDRAM data access rate is good enough for your app. Normally you need burst read and write to improve efficiency.

 

[JingZh Staff Engineer]

Stan, if SDRAM is hard to work with, any experience of using external SRAM?

[StanH Senior Staff Engineer]

SDRAM is not that hard to work with. If you have limited knowledge about it or if it is your first time using it, you can always find some open source SDRAM controller IP as a reference. Also Xilinx and Altera both come with controller core.

As for external SRAM, their mem size is limited. Another tip is try not use async SRAM since it is very sensitive to your interface timing. You may have lots of issues at later stage when you test your system across temperature and voltage.

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