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How to simulate an NGC file in Xilinx FPGA design?

How to simulate an NGC file in Xilinx FPGA design?
2 Voices |4 Posts |1000+ | Discussion Rooom: ASIC and FPGA

This topic contains 3 replies, has 2 voices, and was last updated by  UManish 5 years, 2 months ago.

  • Author
    Posts
  • JGlasrud
    Engineer II

    I received an NGC file for an IP. How to simulate it before imp and test it on FPGA board?

  • UManish
    Staff Engineer

    NGC is netlist. You can implement it and then do post-place & route simulation in Xilinx ISE.

  • JGlasrud
    Engineer II

    Thanks. Is there a way to do pre-place & route simulation on it? I haven’t used post-par simulation yet.

  • UManish
    Staff Engineer

    Post-par simulation is not that hard. But see StanH has a post about sim EDIF file, http://www.valpont.com/how-to-integrate-third-party-ip-hard-macro-into-xilinx-fpga/pst/

    EDIF files can’t be used for simulation directly. Xilinx provides edif2vhdl tool to generate behavioral model vhdl files for sim from IP core’s EDIF file. Edif2vhdl first calls ngdbuild to convert edif to ngd and then calls ngd2vhdl or netgen to convert ngd to vhdl. NGDbuild produces a netlist composed of NGD primitives (Xilinx specific). So after NGDbuild, simulation needs to use SimPrim library rather than UniSim library

    So looks you can do ngc2edif and then follow above to generate vhdl to simulate. Not sure if it works though.

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