EDIF files can’t be used for simulation directly. Xilinx provides edif2vhdl tool to generate behavioral model vhdl files for sim from IP core’s EDIF file. Edif2vhdl first calls ngdbuild to convert edif to ngd and then calls ngd2vhdl or netgen to convert ngd to vhdl. NGDbuild produces a netlist composed of NGD primitives (Xilinx specific). So after NGDbuild, simulation needs to use SimPrim library rather than UniSim library
So looks you can do ngc2edif and then follow above to generate vhdl to simulate. Not sure if it works though.