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Does it really matter if async reset’s deasset edge is not synced?

Does it really matter if async reset’s deasset edge is not synced?

2 Voices |2 Posts |300+ | Discussion Rooom: ASIC and FPGA

This topic contains 1 reply, has 2 voices, and was last updated by Precise-Design 1 year, 1 month ago.

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26/01/2018 05:00

Ravenhill

Thinking maybe most cases are ok. First all ffs get reset. Then when async reset is deasserted, it doesnt meet timing. But ff outpout is not x if reset value and d pin in are the same. Even not the same, two cycles later it settles down. So out of reset, module does not start immediately, it should be ok?
06/12/2019 05:14

Precise-Design

Post count: 1

Good question. It triggers us to write an article about how to do timing check on reset in timed gate sim Should we check async reset timing in timed GLS. But to answer this question directly, it does matter.
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