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Does clock jitter affect hold time

Does clock jitter affect hold time
1 Voices |1 Posts |300+ | Discussion Rooom: ASIC and FPGA

This topic contains 0 replies, has 1 voice, and was last updated by  Trydeman 2 years, 11 months ago.

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  • Trydeman
    Engineer

    debugging a random happening issue with a couple of hw engineers. On scope we notice clock jitter is higher than expected. Setup should be ok but they think hold time may fail. But i thought i read it somewhere clock jitter does not affect hold?

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