Make it to the Right and Larger Audience

Delta Delay in VHDL and Verilog

Resolved Delta Delay in VHDL and Verilog
3 Voices |3 Posts |1000+ | Discussion Rooom: ASIC and FPGA

This topic contains 2 replies, has 3 voices, and was last updated by  yRhoney 5 years, 1 month ago.

  • Author
  • KLiang

    Can someone list what assignments cause delta delay and what do not in VHDL and Verilog? It is important to my design and simulation.


  • JingZh
    Staff Engineer

    I use VHDL. The following is a short slides about delta delay in VHDL. I think basically assigning to signals using <= introduces delta delay while assign to variable using := does not. Not sure about Verilog. I heard it also has delta delay.

  • yRhoney
    Staff Engineer

    For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments cause delta delay.

    Consider the following four models of clock buffers, only clkbuf3 causes delta delay and hence potential hold time issues in RTL sim.





You must be logged in to reply to this topic.

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.



Forgot your details?