ASIC and FPGA

Make it to the Right and Larger Audience

Delta Delay in VHDL and Verilog

Resolved Delta Delay in VHDL and Verilog

3 Voices |3 Posts |1000+ | Discussion Rooom: ASIC and FPGA

This topic contains 2 replies, has 3 voices, and was last updated by yRhoney 5 years, 1 month ago.

Author

Posts
04/12/2015 06:33

KLiang
Engineer

Can someone list what assignments cause delta delay and what do not in VHDL and Verilog? It is important to my design and simulation.

Thanks.
04/12/2015 06:37

JingZh
Staff Engineer

I use VHDL. The following is a short slides about delta delay in VHDL. I think basically assigning to signals using <= introduces delta delay while assign to variable using := does not. Not sure about Verilog. I heard it also has delta delay.
04/12/2015 16:22

yRhoney
Staff Engineer

For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments cause delta delay.

Consider the following four models of clock buffers, only clkbuf3 causes delta delay and hence potential hold time issues in RTL sim.

module clkbuf1 (input a, output z); assign z=a; endmodule

1
2
3

module clkbuf1 (input a, output z);
assign z=a;
endmodule

module clkbuf2 (input a, output z); assign #0 z=a; endmodule

1
2
3

module clkbuf2 (input a, output z);
assign #0 z=a;
endmodule

module clkbuf3 (input a, output reg z); always @(a) z<=a; endmodule

1
2
3

module clkbuf3 (input a, output reg z);
always @(a) z<=a;
endmodule

module clkbuf4 (input a, output reg z); always @(a) z=a; endmodule

1
2
3

module clkbuf4 (input a, output reg z);
always @(a) z=a;
endmodule
Author

Posts

You must be logged in to reply to this topic.

Contact Us

Thanks for helping us better serve the community. You can make a suggestion, report a bug, a misconduct, or any other issue. We'll get back to you using your private message ASAP.

©2021 ValPont.com