I use VHDL. The following is a short slides about delta delay in VHDL. I think basically assigning to signals using <= introduces delta delay while assign to variable using := does not. Not sure about Verilog. I heard it also has delta delay.
For Verilog, only non-blocking assignments cause delta delays. Blocking statements (no matter continuous or procedure assignments), do not cause delta delay. It is unlike in VHDL where all signal assignments cause delta delay.
Consider the following four models of clock buffers, only clkbuf3 causes delta delay and hence potential hold time issues in RTL sim.