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DDR DQS and DQ Timing

DDR DQS and DQ Timing
3 Voices |4 Posts |300+ | Discussion Rooom: ASIC and FPGA

This topic contains 3 replies, has 3 voices, and was last updated by  JingZh 4 years, 8 months ago.

  • Author
    Posts
  • JGlasrud
    Engineer II

    So when read data out of DDR mem, DDR outputs DQS and DQ and their toggling edges are aligned. I assume controller still samples data in the middle of data but how? For write access, DDR mem samples data at DQS toggling edge or in the middle?

  • Lyndsy
    Electrical Engineer

    For read, controller PHY will delay DQS by 90° so that DQS toggles right in the middle of DQ.

    For write, yes, DDR samples DQ at DQS toggling edges.

  • JGlasrud
    Engineer II

    My understand is no matter read or write, DQ(Data) is always aligned with clock edges. For read, DQS 90º adjust is done by controller. For write, DQS adjust is done by DDR memory. Is above right?

  • JingZh
    Staff Engineer

    Correct for read access. For write, actually DQS is aligned with clock and DQ has a 90 degree phase shift since DQS toggles in the middle of DQ.

    Here is a good tutorial about how DDR mem works. Check section 9.

    GDE Error: Error retrieving file – if necessary turn off error checking (404:Not Found)

     

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