Make it to the Right and Larger Audience
This topic contains 0 replies, has 1 voice, and was last updated by MikeD 5 years, 1 month ago.
Let’s say I have a Verilog project and I want to move an instantiated module to somewhere else in design. Anyone knows a tool to do this? We are talking about hundreds of signals to move. Lots of typing to say nothing of verification efforts.
I notice vim has a Verilog mode that may be able to do Verilog auto generation: http://www.vim.org/scripts/script.php?script_id=2372
Anyone used it before? Can it do what I mentioned above?
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