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ASIC and FPGA
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Microcontroller Code Execution and ISP of Flash ROM and RAM
FRANH 02/10/2020 -
Memory Function Path ATE Testing
Wayland Chen 12/08/2019 5 5/5 (1 ) -
Crystal safety margin test and crystal startup time reduction
VinayClark 12/07/2019 5 5/5 (1 ) -
Verification of an Asynchronous Interface Design
Trydeman 02/14/2020 -
UVM for RTL Designers How to Drive Stimulus
dcimple 02/14/2020 -
ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating
Degg12 12/04/2019 3.5 3.5/5 (2 ) -
Debug Memory Read Issue with Timing Analysis and Experiment
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Pendra 02/15/2020
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Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Parker 12/08/2019 4.5 4.5/5 (2 )
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Practical Consideration of Adaptive Voltage Scaling (AVS)
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vlsisuh 02/20/2020 -
Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS
P
Precise-Design 12/06/2019
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SoC Architecture Design Overview
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aaronchi 03/26/2016 -
720P Color Bar Generator Using HDMI Interface to Demo Spartan 6 Video Dev Kit
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GVI_Tech 03/18/2016 -
[Slides] Digital ASIC Backend Process Tutorial for Frontend Engineers
SD-RTL-DGN 03/06/2016 5 5/5 (1 ) -
Low Power Design In Algorithm Level
V
Precise-Design 08/03/2016 4 4/5 (1 ) -
Cadence User Conference 2017 Shanghai, Track5 SoC System Verification
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JamesWan 12/26/2018 -
10G Ethernet MAC Design Example With Xilinx Kintex-7 Dev Kit
GVI_Tech 03/18/2016
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AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code
Precise-Design 03/19/2016 4 4/5 (1 ) -
RS232 UART Verilog Core
Lyndsy 12/01/2015 -
PCIE Gen2 x4 DMA Design Example with Xilinx Kintex-7 Connectivity Kit
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GVI_Tech 03/18/2016 4 4/5 (1 )
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Perl Script to Generate CRC Verilog Code
earnestwu 03/26/2016
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Xilinx and Altera FPGA Expert
JingZh 04/21/2016$30
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FPGA and Digtial IP Design Firm Highly Experienced on PCIE/USB/MIPI
GVI_Tech 04/01/2016
$50
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016
$50
- How do we know if there is a hold violation, x10+, 12/07/2019,
- Does it really matter if async reset’s deasset edge is not synced?, x300+, 12/07/2019,
- Slow Turn-off due to cap discharging consumes extra energy, x150+, 03/21/2019,
- Does clock jitter affect hold time, x300+, 02/21/2018,
- Accuracy of ptpx power analysis, x300+, 02/21/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x300+, 02/21/2018,
Topics
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Hot Chips 2018
MattChiu 01/23/2019 -
Primetime Timing ECO
Ravenhill 01/03/2018 -
Very Detailed Xilinx FPGA Tutorials
JHicks 12/09/2017
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Hot Chips 2017
MattChiu 01/23/2019
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Digital Backend Flow Introduction
JLarson 02/18/2019 -
Hotchips 2016
MattChiu 12/27/2017 4 4/5 (1 )
#INTEL RELEASES ROYALTY-FREE, HIGH-PERFORMANCE AIB INTERCONNECT STANDARD FOR DIE-TO-DIE SIP CONNECTION
Intel is joining CHIPS Alliance to share the Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same…[Read more]
4th wave of #fpga dev, licensing fpga logic to gpu, cpu, asic vendors for datacenter and hpc markets
[Read more]
A #BIST scheme for faster in-system test of automotive ICs
Get this info from Mentor. Interesting content.
Automotive ICs have have strict requirements for in-field and in-system test, including a short test window for key-on, key-off and functional operation. To help designers meet…[Read more]
#Xilinx unveils open source FPGA platform
New Vitis kit from FPGA vendor Xilinx will use familiar languages like C++ and Python for everything from IoT to video encoding.
https://www.networkworld.com/article/3442719/xilinx-unveils-open-source-fpga-platform.html
Early AXI4 SoC Performance Verification Using NVIDIA Matchlib & Catapult SystemC HLS
Tuesday, December 10th @10:00AM US/Pacific
NVIDIA Matchlib is a new open source library that enables much faster design and verification of SoCs using High-Level Synthesis (HLS). One of the primary…[Read more]
Get reset domain crossing RDC right. Mentor webinar.
A new breed of domain crossings introduce challenging issues, including those related to metastability, in the design of ASICs. These #reset domain crossings (RDC) have become more prevalent due to the increase of third party IP,…[Read more]
#axi outstanding and out of order transaction
Good arm reading about this topic.
[Read more]
China increases #EDA software effort for overall chip ambition
sino-us tention only escalates it.
“If you look at the main companies in this software market segment, the average age of many [of their EDA engineers] are like 50 years old now,” Wong said. “So this is an opportunity for C…[Read more]