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ASIC and FPGA
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DFT Logic Power Domain and Related Issues in Multiple Power Domain DFT
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Sarkar 04/20/2019 -
DFT for Low Power Design with Multiple Power Domains
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Sarkar 03/19/2019 -
Code Signing in an Embedded System
sunakm 03/31/2019 -
Integration of ARM PrimeCell PL081 DMA Controller
leonan 04/15/2019 5 5/5 (1 ) -
Convert Existing Design to Low Power Design
P
Precise-Design 03/25/2019 -
An Asynchronous Interface Design without Explicit Cross Clock Domain Synchronizer
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Palak_Nair 04/13/2019 -
ARM Exclusive Access and Semaphore
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enyta 03/29/2019 -
Cortex-M Normal Type Memory and AHB Transaction Reorder
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Bill-Ramsey 04/05/2019 -
Inappropriate Verilog timescale Causes Pulse Timing Check Miss
pgzen 04/09/2019
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ARM Cortex-M System Bus Usage
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Bill-Ramsey 03/29/2019
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[Slides] Digital ASIC Backend Process Tutorial for Frontend Engineers
SD-RTL-DGN 03/06/2016 5 5/5 (1 ) -
10G Ethernet MAC Design Example With Xilinx Kintex-7 Dev Kit
GVI_Tech 03/18/2016 -
Cadence User Conference 2017 Shanghai, Track5 SoC System Verification
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JamesWan 12/26/2018 -
720P Color Bar Generator Using HDMI Interface to Demo Spartan 6 Video Dev Kit
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GVI_Tech 03/18/2016 -
SoC Architecture Design Overview
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aaronchi 03/26/2016 -
Low Power Design In Algorithm Level
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Precise-Design 08/03/2016 4 4/5 (1 )
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RS232 UART Verilog Core
Lyndsy 12/01/2015 -
Perl Script to Generate CRC Verilog Code
earnestwu 03/26/2016 -
AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code
Precise-Design 03/19/2016 4 4/5 (1 ) -
PCIE Gen2 x4 DMA Design Example with Xilinx Kintex-7 Connectivity Kit
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GVI_Tech 03/18/2016 4 4/5 (1 )
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Xilinx and Altera FPGA Expert
JingZh 04/21/2016$30
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FPGA and Digtial IP Design Firm Highly Experienced on PCIE/USB/MIPI
GVI_Tech 04/01/2016
$50
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016
$50
- Slow Turn-off due to cap discharging consumes extra energy, x150+, 03/28/2019,
- Does clock jitter affect hold time, x150+, 02/25/2018,
- Accuracy of ptpx power analysis, x150+, 02/25/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x150+, 02/25/2018,
- Does it really matter if async reset’s deasset edge is not synced?, x150+, 02/25/2018,
- Verilog test BFM to drive and monitor internal AHB bus, x1000+, 09/25/2016,
Topics
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Hot Chips 2018
MattChiu 01/23/2019 -
Hotchips 2016
MattChiu 12/27/2017 4 4/5 (1 ) -
Hot Chips 2017
MattChiu 01/23/2019
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Primetime Timing ECO
Ravenhill 01/03/2018 -
Very Detailed Xilinx FPGA Tutorials
JHicks 12/09/2017
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Digital Backend Flow Introduction
JLarson 02/18/2019
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Indium arsenide channel transistors for mm-wave and high-speed applications
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Industrial HMI in a package
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Silvaco’s device simulator selected by FLOSFIA for developing GaO power devices
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Midsummer’s revenue grows 90% in 2018
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Anokiwave introduces second set of intelligent gain block ICs in family of mmWave multi-market solutions
HLS for Vision and Deep Learning Hardware Accelerators Seminar
Biltmore Hotel
Santa Clara, CA
May 7th, 2019
9:00 AM – 4:00 PM
Holiday Inn Spectrum
Irvine, CA
May 9th, 2019
9:00 AM – 4:00 PM
Deep learning applications are exploding, especially those that use images for computer vis…[Read more]
Use #lbist and #mbist for in field test
Lbist and mbist are commonly used for chip manufacturing test. But they can be and is being used in infield test.
There are defects which may appear during the field operation of device. The infield failures are mainly because of latent faults which…[Read more]
Facebook plans to design its own chip, likely for #AI
The social media company is seeking to hire a manager to build an “end-to-end SoC/ASIC, firmware and driver development organization,” Facebook could use such chips to power hardware devices, artificial intelligence software and ser…[Read more]
Don’t forget to swap memory behavioral model with #Xilinx #Coregen model when do FPGA synthesis
An intern wrote a small block. When synthesize the whole design with this new block using Xilinx #Vivado, it take way longer time to finish. It turns out his block has a big size memory. He…[Read more]
40 GPUs on a single silicon wafer to lower interconnect power
#Interconnect can be done at board level, #package level, and wafer level. “Silicon interconnect fabric” employs wafer level connection.
[Read more]
Chip design is PPT ?!
Chip business is Powerpoint? Yes, BP IS PPT:
B: Business model
P: Product definition
I: IP design and qualification
S: System integration
P: Physical design
P: Package design
T: Test
How IBM handles L3/L4 #memory #cache in power8, power9, and power10
[Read more]