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In ASIC/SOC Which Area is More Promising for Young Chip Engineers

Promising Areas

  • Simulation and Verification
  • SOC Integration
  • SOC IP Design
  • DFT
  • Backend PrimeTime and Synthesis
  • Backend Place and Routing
  • Others

Maximum 0 options allowed

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  • #Xilinx unveils open source FPGA platform

    New Vitis kit from FPGA vendor Xilinx will use familiar languages like C++ and Python for everything from IoT to video encoding.

  • Group logo of ASIC and FPGADRama posted 1 month, 1 week ago · , 0, 0

    Early AXI4 SoC Performance Verification Using NVIDIA Matchlib & Catapult SystemC HLS
    Tuesday, December 10th @10:00AM US/Pacific

    NVIDIA Matchlib is a new open source library that enables much faster design and verification of SoCs using High-Level Synthesis (HLS). One of the primary…[Read more]

  • Group logo of ASIC and FPGADRama posted 1 month, 1 week ago · , 0, 0

    Get reset domain crossing RDC right. Mentor webinar.

    A new breed of domain crossings introduce challenging issues, including those related to metastability, in the design of ASICs. These #reset domain crossings (RDC) have become more prevalent due to the increase of third party IP,…[Read more]

  • #axi outstanding and out of order transaction

    Good arm reading about this topic.

    [Read more]

  • China increases #EDA software effort for overall chip ambition

    sino-us tention only escalates it.

    “If you look at the main companies in this software market segment, the average age of many [of their EDA engineers] are like 50 years old now,” Wong said. “So this is an opportunity for C…[Read more]

  • CHIPS Alliance, an open source hardware association

    Formed early this year, CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.

    CHIPS Alliance aims to host implementation efforts…[Read more]

  • Designing and Benchmarking of Double-Row Height Standard Cells

    Still not sure why “Note that a double-row height cell uses M2 P/G rails rather than M1 P/G rails. The reason for this is “. But a good reading for #standardcell.

    Double height cells can use the
    region underneath the P/G rail…[Read more]

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