ASIC and FPGA

Make it to the Right and Larger Audience

In ASIC/SOC Which Area is More Promising for Young Chip Engineers


Promising Areas

  • Simulation and Verification
  • SOC Integration
  • SOC IP Design
  • DFT
  • Backend PrimeTime and Synthesis
  • Backend Place and Routing
  • Others

Maximum 0 options allowed

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  • #INTEL RELEASES ROYALTY-FREE, HIGH-PERFORMANCE AIB INTERCONNECT STANDARD FOR DIE-TO-DIE SIP CONNECTION

    Intel is joining CHIPS Alliance to share the Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same…[Read more]

  • Group logo of ASIC and FPGAFRANH posted 1 week, 4 days ago · , 0, 0

    4th wave of #fpga dev, licensing fpga logic to gpu, cpu, asic vendors for datacenter and hpc markets

    [Read more]

  • Group logo of ASIC and FPGASarkar posted 3 weeks, 3 days ago · , 0, 0

    A #BIST scheme for faster in-system test of automotive ICs

    Get this info from Mentor. Interesting content.

    Automotive ICs have have strict requirements for in-field and in-system test, including a short test window for key-on, key-off and functional operation. To help designers meet…[Read more]

  • #Xilinx unveils open source FPGA platform

    New Vitis kit from FPGA vendor Xilinx will use familiar languages like C++ and Python for everything from IoT to video encoding.

    https://www.networkworld.com/article/3442719/xilinx-unveils-open-source-fpga-platform.html

  • Early AXI4 SoC Performance Verification Using NVIDIA Matchlib & Catapult SystemC HLS
    Tuesday, December 10th @10:00AM US/Pacific

    NVIDIA Matchlib is a new open source library that enables much faster design and verification of SoCs using High-Level Synthesis (HLS). One of the primary…[Read more]

  • Get reset domain crossing RDC right. Mentor webinar.

    A new breed of domain crossings introduce challenging issues, including those related to metastability, in the design of ASICs. These #reset domain crossings (RDC) have become more prevalent due to the increase of third party IP,…[Read more]

  • Group logo of ASIC and FPGAJLarson posted 5 months ago · , 0, 0

    #axi outstanding and out of order transaction

    Good arm reading about this topic.

    [Read more]

  • China increases #EDA software effort for overall chip ambition

    sino-us tention only escalates it.

    “If you look at the main companies in this software market segment, the average age of many [of their EDA engineers] are like 50 years old now,” Wong said. “So this is an opportunity for C…[Read more]





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