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ASIC and FPGA
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Discussion of ” A simple way to estimate the total power consumption of memories in an SoC”
Yicheng 09/09/2019 -
SoC IO Pad, Bump, Ball, and Pin
entcag 09/22/2019 -
Isolation Low and High Cells for SoC Low Power Design
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peterSze 09/07/2019 -
Several Techniques to Reduce Memory Block Current Consumption
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Arcis 08/18/2019 -
Body Biasing and PFET Nwell Connection
FRANH 09/10/2019 -
Case study: how to insert logic on cross hardmacro signal properly with power domain consideration
P
Precise-Design 09/09/2019 -
An Intrinsically Secure Processor and A Software Based Security Approach
elwood-speth 08/16/2019 -
PEM and OBIRCH, Bright Spot Failure Analysis for Flip Chip
nedge 08/17/2019 -
Issues and Solutions of Formality Formal Verification for Beginners
LarryB 08/19/2019 5 5/5 (1 ) -
Use VCLP and UPF to report power domain crossing signals
PoojaV 09/18/2019
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10G Ethernet MAC Design Example With Xilinx Kintex-7 Dev Kit
GVI_Tech 03/18/2016 -
SoC Architecture Design Overview
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aaronchi 03/26/2016 -
720P Color Bar Generator Using HDMI Interface to Demo Spartan 6 Video Dev Kit
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GVI_Tech 03/18/2016 -
[Slides] Digital ASIC Backend Process Tutorial for Frontend Engineers
SD-RTL-DGN 03/06/2016 5 5/5 (1 ) -
Low Power Design In Algorithm Level
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Precise-Design 08/03/2016 4 4/5 (1 ) -
Cadence User Conference 2017 Shanghai, Track5 SoC System Verification
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JamesWan 12/26/2018
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RS232 UART Verilog Core
Lyndsy 12/01/2015 -
PCIE Gen2 x4 DMA Design Example with Xilinx Kintex-7 Connectivity Kit
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GVI_Tech 03/18/2016 4 4/5 (1 )
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AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code
Precise-Design 03/19/2016 4 4/5 (1 ) -
Perl Script to Generate CRC Verilog Code
earnestwu 03/26/2016
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016$50
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Xilinx and Altera FPGA Expert
JingZh 04/21/2016
$30
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FPGA and Digtial IP Design Firm Highly Experienced on PCIE/USB/MIPI
GVI_Tech 04/01/2016
$50
- Slow Turn-off due to cap discharging consumes extra energy, x150+, 03/23/2019,
- Does clock jitter affect hold time, x300+, 02/13/2018,
- Accuracy of ptpx power analysis, x150+, 02/13/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x300+, 02/13/2018,
- Does it really matter if async reset’s deasset edge is not synced?, x300+, 02/13/2018,
- Verilog test BFM to drive and monitor internal AHB bus, x1000+, 09/13/2016,
Topics
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Very Detailed Xilinx FPGA Tutorials
JHicks 12/09/2017 -
Hotchips 2016
MattChiu 12/27/2017 4 4/5 (1 ) -
Primetime Timing ECO
Ravenhill 01/03/2018 -
Digital Backend Flow Introduction
JLarson 02/18/2019 -
Hot Chips 2017
MattChiu 01/23/2019
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Hot Chips 2018
MattChiu 01/23/2019
#axi outstanding and out of order transaction
Good arm reading about this topic.
[Read more]
China increases #EDA software effort for overall chip ambition
sino-us tention only escalates it.
“If you look at the main companies in this software market segment, the average age of many [of their EDA engineers] are like 50 years old now,” Wong said. “So this is an opportunity for C…[Read more]
CHIPS Alliance, an open source hardware association
Formed early this year, CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
CHIPS Alliance aims to host implementation efforts…[Read more]
Designing and Benchmarking of Double-Row Height Standard Cells
Still not sure why “Note that a double-row height cell uses M2 P/G rails rather than M1 P/G rails. The reason for this is “. But a good reading for #standardcell.
Double height cells can use the
region underneath the P/G rail…[Read more]
#Hotchips 2019 key notes from AMD CEO Dr. Lisa Su
https://www.anandtech.com/show/14762/hot-chips-31-keynote-day-1-dr-lisa-su-ceo-of-amd-live-blog-145pm-pt
0.1nm in 2050, #Hotchips 2019 key notes from TSMC VP Dr. Phillip Wong
https://www.anandtech.com/show/14770/hot-chips-31-keynote-day-2-dr-phillip-wong-vp-research-at-tsmc-145pm-pt
Large chip for #ai
The size as a ipad, 50x the previous largest chip.
[Read more]
#tsmc improves 7nm process
[Read more]