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ASIC and FPGA
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SoC IO Pad, Bump, Ball, and Pin
entcag 09/22/2019 3.5 3.5/5 (2 ) -
Crystal safety margin test and crystal startup time reduction
VinayClark 12/07/2019 5 5/5 (1 ) -
Transmission Gate Not to be Used on Voltage Domain Boundary
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JLarson 12/03/2019 4 4/5 (1 ) -
Memory Function Path ATE Testing
Wayland Chen 12/08/2019 5 5/5 (1 ) -
Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS
P
Precise-Design 12/06/2019 -
Verilog Initial Block Retriggering at Power up for RTL UPF Simulation
Parker 12/08/2019 4.5 4.5/5 (2 ) -
Use VCLP and UPF to report power domain crossing signals
PoojaV 09/18/2019 4 4/5 (1 )
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ASIC Memory Low Power: Single Rail, Split Rail, and Low Power Modes
Degg12 12/04/2019 3 3/5 (1 ) -
ASIC Memory Low Power: Memory Standby Mode and Memory Clock Gating
Degg12 12/04/2019 3.5 3.5/5 (2 ) -
Case study: how DFT output dedicated isolation cell causes issue in Burn-In test
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AnkitKumar 12/03/2019 4.5 4.5/5 (2 )
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720P Color Bar Generator Using HDMI Interface to Demo Spartan 6 Video Dev Kit
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GVI_Tech 03/18/2016 -
Low Power Design In Algorithm Level
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Precise-Design 08/03/2016 4 4/5 (1 ) -
[Slides] Digital ASIC Backend Process Tutorial for Frontend Engineers
SD-RTL-DGN 03/06/2016 5 5/5 (1 ) -
Cadence User Conference 2017 Shanghai, Track5 SoC System Verification
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JamesWan 12/26/2018 -
SoC Architecture Design Overview
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aaronchi 03/26/2016 -
10G Ethernet MAC Design Example With Xilinx Kintex-7 Dev Kit
GVI_Tech 03/18/2016
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RS232 UART Verilog Core
Lyndsy 12/01/2015 -
PCIE Gen2 x4 DMA Design Example with Xilinx Kintex-7 Connectivity Kit
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GVI_Tech 03/18/2016 4 4/5 (1 )
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AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code
Precise-Design 03/19/2016 4 4/5 (1 ) -
Perl Script to Generate CRC Verilog Code
earnestwu 03/26/2016
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016$50
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Xilinx and Altera FPGA Expert
JingZh 04/21/2016
$30
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FPGA and Digtial IP Design Firm Highly Experienced on PCIE/USB/MIPI
GVI_Tech 04/01/2016
$50
- How do we know if there is a hold violation, x10+, 12/10/2019,
- Does it really matter if async reset’s deasset edge is not synced?, x300+, 12/10/2019,
- Slow Turn-off due to cap discharging consumes extra energy, x150+, 03/27/2019,
- Does clock jitter affect hold time, x300+, 02/17/2018,
- Accuracy of ptpx power analysis, x150+, 02/17/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x300+, 02/17/2018,
Topics
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Hotchips 2016
MattChiu 12/27/2017 4 4/5 (1 ) -
Very Detailed Xilinx FPGA Tutorials
JHicks 12/09/2017 -
Hot Chips 2018
MattChiu 01/23/2019
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Primetime Timing ECO
Ravenhill 01/03/2018 -
Digital Backend Flow Introduction
JLarson 02/18/2019 -
Hot Chips 2017
MattChiu 01/23/2019
#Xilinx unveils open source FPGA platform
New Vitis kit from FPGA vendor Xilinx will use familiar languages like C++ and Python for everything from IoT to video encoding.
https://www.networkworld.com/article/3442719/xilinx-unveils-open-source-fpga-platform.html
Early AXI4 SoC Performance Verification Using NVIDIA Matchlib & Catapult SystemC HLS
Tuesday, December 10th @10:00AM US/Pacific
NVIDIA Matchlib is a new open source library that enables much faster design and verification of SoCs using High-Level Synthesis (HLS). One of the primary…[Read more]
Get reset domain crossing RDC right. Mentor webinar.
A new breed of domain crossings introduce challenging issues, including those related to metastability, in the design of ASICs. These #reset domain crossings (RDC) have become more prevalent due to the increase of third party IP,…[Read more]
#axi outstanding and out of order transaction
Good arm reading about this topic.
[Read more]
China increases #EDA software effort for overall chip ambition
sino-us tention only escalates it.
“If you look at the main companies in this software market segment, the average age of many [of their EDA engineers] are like 50 years old now,” Wong said. “So this is an opportunity for C…[Read more]
CHIPS Alliance, an open source hardware association
Formed early this year, CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
CHIPS Alliance aims to host implementation efforts…[Read more]
Designing and Benchmarking of Double-Row Height Standard Cells
Still not sure why “Note that a double-row height cell uses M2 P/G rails rather than M1 P/G rails. The reason for this is “. But a good reading for #standardcell.
Double height cells can use the
region underneath the P/G rail…[Read more]
#Hotchips 2019 key notes from AMD CEO Dr. Lisa Su
https://www.anandtech.com/show/14762/hot-chips-31-keynote-day-1-dr-lisa-su-ceo-of-amd-live-blog-145pm-pt