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ASIC and FPGA
Digital ASIC and FPGA RTL design, verification, backend timing/PAR/DFT process, test, bring-up and debug.
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PCIE Tutorial: Hardware Oriented ASPM Link State and L1 Substates
SD-RTL-DGN 03/13/2018 4 4/5 (1 ) -
ARM Cortex-M Processor Low Power
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Bill-Ramsey 03/15/2018 -
Timing and Clock, How DFT and BE can Mess up your Design
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Palak_Nair 02/10/2018 -
Case Study: How to Use Internal PLL as DFT Test Clock
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AnkitKumar 12/02/2018 -
PCIE Tutorial: How to Test in Linux
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SD-RTL-DGN 03/14/2018 4 4/5 (1 ) -
ARM ESL SOCDesigner Modeling and Simulation
jQiu 02/10/2018 -
Power Supply Connection in Low Power Design
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Precise-Design 02/25/2018 -
PCIE Tutorial: Software Initiated Device Power Management
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SD-RTL-DGN 03/11/2018 -
Clock Gating and Muxing on Xilinx FPGA
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FRANH 03/26/2018 -
Reset ARM subsystem in Single Core and Multiple Core System May Not be Easy
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Bill-Ramsey 02/11/2018
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720P Color Bar Generator Using HDMI Interface to Demo Spartan 6 Video Dev Kit
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GVI_Tech 03/18/2016 -
SoC Architecture Design Overview
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aaronchi 03/26/2016 -
[Slides] Digital ASIC Backend Process Tutorial for Frontend Engineers
SD-RTL-DGN 03/06/2016 5 5/5 (1 ) -
Low Power Design In Algorithm Level
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Precise-Design 08/03/2016 4 4/5 (1 ) -
10G Ethernet MAC Design Example With Xilinx Kintex-7 Dev Kit
GVI_Tech 03/18/2016
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RS232 UART Verilog Core
Lyndsy 12/01/2015 -
AHB based SDRAM Buffering Design with AHB SDRAM Controller Verilog Code
Precise-Design 03/19/2016 4 4/5 (1 ) -
Perl Script to Generate CRC Verilog Code
earnestwu 03/26/2016 -
PCIE Gen2 x4 DMA Design Example with Xilinx Kintex-7 Connectivity Kit
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GVI_Tech 03/18/2016 4 4/5 (1 )
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Xilinx and Altera FPGA Expert
JingZh 04/21/2016$30
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Veteran ASIC/FPGA RTL Design Team
SD-RTL-DGN 02/01/2016
$50
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FPGA and Digtial IP Design Firm Highly Experienced on PCIE/USB/MIPI
GVI_Tech 04/01/2016
$50
- Slow Turn-off due to cap discharging consumes extra energy, x80+, 03/05/2018,
- Does clock jitter affect hold time, x150+, 02/05/2018,
- Accuracy of ptpx power analysis, x80+, 01/29/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x150+, 01/29/2018,
- Does it really matter if async reset’s deasset edge is not synced?, x150+, 01/29/2018,
- Verilog test BFM to drive and monitor internal AHB bus, x1000+, 09/12/2016,
Topics
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An Introduction to SystemVerilog
Abhikarsh 08/18/2016 -
Hotchips 2016
MattChiu 12/27/2017 4 4/5 (1 ) -
Very Detailed Xilinx FPGA Tutorials
JHicks 12/09/2017 -
An Introduction to Verilog
jQiu 08/18/2016 -
Primetime Timing ECO
Ravenhill 01/03/2018 -
[Book] FPGA-Based Implementation of Signal Processing Systems
KLiang 08/14/2016
[Read more]
How to force VHDL signal in simulation
Lack of signal force support in VHDL is really a headache to verification engineers. Unfortunately I ran into this issue recently. A signal in VHDL has to be forced in test bench or I have to hack VHDL which is obviously not desired. Amid quite a bit…[Read more]
Synopsys DC doesn’t optimize timing?
Get timing report from timing team. Surprise to see DC uses high delay cells which make the path failing the constraint by quite a bit. DC can easily use low delay cells to fix it. STA tool can fix it anyway. What really concerns me here is if DC takes…[Read more]
#dft difference of #Synchronous #reset and async reset
Sync abd async reset have their pros and cons. Rtl point of view, one signal can be connected to both async reset and sync reset. This is not true for dft. You will see async reset has one extra dft mux on the sync reset to add in dft…[Read more]
#Synthesis reports FFs without #clock?
Check your clock constraints if so. Most cases it is not rtl issue. FFs are connected to a clock. But this clock is not defined in clock constraints. Synthesis and STA treat it as no clock since no clock information is available.
#Fpga programing #spi #flash
The idea is to send data from pc to fpga and then from fpga to spi flash. Pc to fpga communication can be done with uart. Fpga then implements an spi master module which converts uart data to spi data sent to flash from spi master module.
In fact, lots of…[Read more]
Synopsys buys kilopass to strengthen its IP pool
Kilopass offers one time programmable NVM. Synopsys is another big player in IP business other than ARM
[Read more]
Vivado #HLS finally works
Successfully used vivado HLS to synthesize cpp project into hw ip and havve it running on xilinx fpga. Note i said hw ip instead of rtl because generated rtl calls other xilinx cores which may further use other ips. There is NO file list to locate all the rtl…[Read more]