- How do we know if there is a hold violation, x150+, 12/19/2019,
- Does it really matter if async reset’s deasset edge is not synced?, x300+, 12/19/2019,
- Slow Turn-off due to cap discharging consumes extra energy, x300+, 04/19/2019,
- Does clock jitter affect hold time, x300+, 02/19/2018,
- Accuracy of ptpx power analysis, x300+, 02/19/2018,
- Stitch two scan chains of different clock domains make timing closure worse?, x300+, 02/19/2018,
Topics
Arm Offers Free Up-Front Access to Small Startups
With the new aspect of the program, early-stage startups can access a range of Arm IP at no cost, allowing them to experiment, design and prototype with various Arm solutions throughout the product development cycle, the company…[Read more]
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AI assisted #backend EDA tool
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Mentor webinar covering Catapult HLS for AI, ML, and IoT
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Excellent short article about process variation, OCV, and library characterization
#backend
A glimpse of TSMC 5nm node
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#INTEL RELEASES ROYALTY-FREE, HIGH-PERFORMANCE AIB INTERCONNECT STANDARD FOR DIE-TO-DIE SIP CONNECTION
Intel is joining CHIPS Alliance to share the Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same…[Read more]