Recently I am studying whether to connect grounds inside a chip with multiple power domains and if not what is the impact on ESD protection. Searched web and found some good tutorials about ESD protection, IO clamp, power clamp, etc. But the discussion to this topic is not clear. Here is what I figured out based on my research.
First, let’s look at what is the issue. Below diagram shows a typical ESD protection scenario in an ASIC.
The following is site premium content.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Use points to gain access. You can either purchase points or contribute content and use contribution points to gain access.
Highlights: 698 words, 2 images
Groups:
Tags:
