How UPF model retention flip flop?

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How UPF model retention flip flop?
3 Voices |3 Posts |300+ | Discussion Rooom: Low Power

This topic contains 2 replies, has 3 voices, and was last updated by  Precise-Design 3 years ago.

  • Author
  • PoojaV
    Senior Engineer

    I m confused about how UPF model retention flip flop. If a flip flop is retained, why its output becomes x? Ff is retained right?

    in addition, retention is out of x when power is reapplied or when retention condition is false?

    I am using questa.

  • DRama
    Master student
    Post count: 1

    I am using Questa too. I notice retention flip flop is out of x when power is back on and before retention control toggles to non-retain mode.

  • Precise-Design
    Post count: 1

    DRama is correct. That is expected behavior for both sim and silicon. Reason is related to how retention FF works. Below is a typical master-slave FFs. A typical retention FF is when main VDD is gone, only slave latch keeps power so it can hold FF content. But of course since no need to capture new data, the voltage to drive slave latch can be much lower and just enough to hold data. Key is that buffer on Q is also powered down. This is why in retention FF output is x. But when main power is reapplied, that buffer on Q is active and slave latch output can be properly driven out so FF out is out of x.


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