How to handle WID when connect AXI4 master to AXI3 bus?

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Resolved How to handle WID when connect AXI4 master to AXI3 bus?
3 Voices |4 Posts |1000+ | Discussion Rooom: AMBA, AXI, ACE, AHB, APB

This topic contains 3 replies, has 3 voices, and was last updated by  pedrotrost 4 years, 5 months ago.

  • Author
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  • pedrotrost
    Senior Engineer
    Post count: 1

    AXI3 has WID signals but it is removed in AXI4. Now I have a AXI4 bus master. How do I connect it to AXI3 bus since the latter has WID IOs. Just tie them to zero is ok?

    BTW, if it is the other way around (AXI3 master toAXI4 bus), just leave AXI3 master WID unconnected?

  • RGhosh
    Post count: 2

    Write data interleave is removed in AXI4 so no need for WID. It needs some user logic if we’d like to hook up AXI4 master to AXI3 bus. I don’t think we can just tie AXI3 bus WID to some fixed value like 0 since AXI3 will get confused that multiple transactions belongs to different writes have the same WID. I think user logic needs to generate WID and then send it along with AXI4 write data to AXI3 bus.

  • RegW
    Senior Engineer
    Post count: 1

    AXI4 still keeps AWID for write address channel. Can we just reuse AWID as the WID and hook it up to AXI3 bus?

  • pedrotrost
    Senior Engineer
    Post count: 1

    I see. I could generate WID or reuse AWID as it seems convenient. But if AW comes before write data, I need to buffer AWID first and based on master issuing capability I may need to buffer multiple AWID’s. In addition, if write data comes before AW, I can’t send it out since I don’t know AWID for this write data yet. So using AWID may not be convenient.

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