Generate netlist with n-well and p-well connect for sign-off LVS

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Generate netlist with n-well and p-well connect for sign-off LVS
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This topic contains 0 replies, has 1 voice, and was last updated by  yendtvt 2 months, 1 week ago.

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  • Currently, I am facing the issue that:

    – out of data pin, p/g pins, standard cells have n-well, p-well and substrate terminal also. In the document they are specified to connect to 1’b1 or 1’b0 respectively.

    – when generate verilog netlist for LVS, we applied -pg option but we could not see connection of those n-well, p-well, substrate terminal. It cause the wrong spice netlist later on.

    Just want to ask your advise in case you have similar issue before.

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