In this tutorial, we talk about exception and interrupt handling with ARM processors.

This tutorial has a heavy focus on arm processors which is the most popular processor family in mobile, embedded, and low power domain.

It is a 67-page slides.

The following are some of the topics touched.
vector table and general exception handling procedure

When an exception occurs, the ARM:
1. Copies CPSR into SPSR_<mode>
2.Sets appropriate CPSR bits
If core currently in Thumb state then ARM state is entered
Mode field bits
Interrupt disable bits (if appropriate)
3. Stores the return address in LR_<mode>
4. Sets PC to vector address
Different for v6 with vectored interrupts – see later

To return, exception handler needs to:
1. Restore CPSR from SPSR_<mode>
2. Restore PC from LR_<mode>

Exception table instructions:
Branch Instruction
Direct branch always to handler address label
The handler must be within 32MB of the branch instruction, which may not be possible with some memory organizations
Move PC instruction
Directly load the PC with a handler address label located on applicable address boundary
Address must be able to be stored in 8-bits, rotated right an even number of places
Load PC instruction
The PC is forced directly to the handler’s address by
Storing the address in a suitable memory location (within 4KB of the vector address).
Loading the vector with an instruction which loads the PC with the contents of the chosen memory location.

FIR vs IRQ and interrupt handling in C

Some common issues such as stack issue and nested interrupt issue.

 
A brief mentioning of vectored interrupt controller.

Details about special exceptions such as reset, SWI, software interrupt, etc.

The full 67-page slides is as below.

 

Lakeside Embedded Technologies

Lakeside Embedded Technologies is an embedded system design firm. We offer first class firmware design service based on our deep understanding of ARM processors and its hardware/software architectures. We also offer online and onsite ARM firmware trainings.