Date(s) - 05/19/2020 - 05/21/2020
Your registration will register you for both day 1 & 2, although the confirmation email will state that you are only registered for day 2
In the last few years, our HLS full day seminars have been live events with tremendous positive feedback for both the technical value of the material and the beneficial interaction with subject matter experts. As live events are not possible right now, we have been looking for a new way to bring both the material and the in-person experience to you, virtually, in a completely live format. As a result, we have split the content into two 2-3 hr sessions running over 2 days. We will have interactive breakout sessions where you can join the presenters for live Q&A in addition to the ability for you to both type/chat and or ask live questions during the presentations. We look forward to your feedback on this new format and our new content.
Catapult HLS (High-Level Synthesis) is being used in production today in everything from performance critical 5G/Communication and Image/Video Processing designs to the lowest power edge AI/ML enabled designs and IP. Teams using HLS are consistently able to deal with frequently changing specifications and still cut project times for design and verification by more than half in both FPGA and ASIC implementations. This technical seminar will step through how HLS can address these challenges using an example smart IoT application requiring AI/ML Computer Vision capabilities at the lowest possible power.
Agenda – DAY 1
|30MIN||HLS Introduction and Customer Case Studies|
|15MIN||Break & Live Q&A Rooms|
|30MIN||Introducing 2-D Convolution for AI/ML Algorithms and Applications|
|30MIN||Introduction to Modeling Performance and Verification with Synthesizable MatchLib|
|30MIN||Silexica: Accelerating the Journey from C/C++ to ASIC|
|15MIN||Day 1 Summary and Day 2 Preview|
Agenda – DAY 2
|15MIN||Recap of Day 1|
|40MIN||Optimizing for Power/Performance/Area with HLS|
|30MIN||Arm: IoT SoC Solutions with Corstone|
|30MIN||System Integration and Measuring Energy|
|15MIN||Live Q&A & Prize Drawing|
What You Will Learn
- What is the status of HLS today, how are customers using it and what HLS IP, example designs and technical resources are available to come up to speed quickly.
- The basics of how HLS works and how designers can meet timing and area targets while writing their design in C++/SystemC.
- How HLS can be used to optimize hardware architectures for an energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
- How to use a new HLS synthesizable library called MatchLib to do early and accurate performance modeling for complex control logic and systems and enable verification.
- How ecosystem partners such as Arm and Silexica can further accelerate the path from algorithm to working system.
Who Should Attend
- RTL Designers or Project Managers interested in moving up to HLS to significantly improve design and verification productivity.
- Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in creating energy-efficient accelerators.
- New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP.