Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS

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Does it matter if async reset deassert edge is not synced and Should we check async reset timing in timed GLS

This post is triggered by Ravenhill’s question Does it really matter if async reset’s deasset edge is not synced?

Here is the argument, “Thinking maybe most cases are ok. First all ffs get reset. Then when async reset is deasserted, it doesnt meet timing. But ff outpout is not x if reset value and d pin in are the same. Even not the same, two cycles later it settles down. So out of reset, module does not start immediately, it should be ok?”

Short answer is async reset has to be deasserted synchronously. In other words, deassertion edge needs to meet setup/hold timing relative to flip-flop clock. There are several issues with the argument.

  1. “But ff outpout is not x if reset value and d pin in are the same”. This is true but not guaranteed by design.
  2. “Even not the same, two cycles later it settles down. So out of reset, module does not start immediately, it should be ok?”  It is not true two cycles later x will be gone. We are not talking about one FF here. Other FFs are also x out of reset. So module likely will stay in x. I am not sure what “out of reset, module does not start immediately” means. I think it means although x shows up for some time, if that signal is not used or won’t propagate, it should be good. It sounds can work but again not guaranteed by design.

 

Then if we think one step further, here come some interesting questions. We all know to run timed (sdf back-annotated) gate level simulation, we need to come up with a flip-flop list that we should not check timing. Why? Because we have to take care of 2-FF synchronizers in design. The 1st stage of 2-FF synchronizer does not need to meet timing. If we don’t disable timing check on the 1st stage FF, it will be x in timed GLS and x will propagate and mess up the sim. So we disable timing check on d pin of the 1st stage FF. But if the 1st stage FF has a async reset pin, shall we disable timing check on it too? Remember, async reset’s assert edge is async and deassert edge is sync. If we check, does it create x? If we don’t check, does it hide issue? We will explain why either way may be fine. We will also show you in one special case we do NOT want to check otherwise it will cause issue in sim.

 

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