Digital IC Backend Lab showing the whole BE Process

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Digital IC Backend Lab showing the whole BE Process

Here we use a simple RTL design to go through the whole backend process, including synthesis, floorplan, placement, CTS, routing, route_opt, and DFM (chip finish). Detailed tcl scripts are given. Synthesis and floorplan are discussed in page 1 and others in page 2.

 

 

 
Senior Engineer
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1 Comment
  1. mazhar 3 months ago
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    Thanks so much

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