When we do IR drop analysis, we would like to use the worst case current. The next question is which mode has the worst current, func mode, dft scan shift mode, or dft capture mode.
It is easy to understand dft mode has worse current than func mode since in dft mode more FFs toggle at the same time. But it may not be that straightforward to understand dft scan shift mode has worse current than dft capture mode. Two argument to favor capture mode are
- capture clock can be much faster than shift clock.
- in capture mode not only FFs toggle but also combinational logic toggle while in shift mode only FFs toggle.
For #1, true capture clock is normally faster than shift clock. Shift clock is generally like 10Mhz and 20Mhz. Capture clock depends on design and can be 200Mhz/400Mhz for at speed test. But what IR drop analysis cares is instantaneous current which refers to current draw around clock rising edge so clock rate doesn’t matter.
For #2, it is in fact not true combinational logic does not toggle in DFT scan shift mode. Here shows how FFs and comb logic are connected in func and dft mode. In func mode, TE (test enable) pin of DFF is 0 so d goes to q. In scan shift mode, TE=1 so q is driven by TI and not by d. Simply speaking, DFF clock has three sources, shift clock for scan shift mode, capture clock for dft capture mode, and func clk for func mode.
In scan shift mode, shift_clk drives DFF. DFF q is driven by TI because TE=1. But it is important to notice q still drives comb logic and there is no isolation to block q from driving comb logic. So during shift, q toggles and comb logic toggles as a result. This is also why we normally see there is an isolation layer to protect analog module from randomly toggled digital inputs during scan shift mode.
So we ask DFT engineer to run ATPG scan shift simulation and generate a waveform for IR drop analysis. Based on the waveform window, IR drop analysis can report instantaneous current level and IR drop for logic modules and power domains. We normally set a threshold say if IR drop is less than certain percentage of supply level, we can accept this IR drop level. This percentage can be 15%, 20%, 25% depending on your project.
Let’s say IR drop is unfortunately beyond the threshold. What can you do to improve IR drop? You can check if power distribution mesh network can be improvement to reduce IR drop with the same level of current, if number of power switches can be increased to reduce IR drop across power switches.
Another way is try to reduce current.
First, when we generate vector, we can ask ATPG tool to have less FF toggling. Of course this comes with penalty, less test coverage and longer test time.
Second, recall large current in scan shift mode is due to lots of FFs and comb logic toggle around the same time (the same clock edge) as shown in below diagram. Is there a way to stagger clock edges to reduce the instantaneous current?
Indeed. We insert an clock delay cell on scan shift clock. Each scan chain can have a dedicated clock delay cell. Delay of clock delay cell can be programmable so during shift mode, we can program these delay cells to have different delays to stagger shift clock toggling edge.
Above scan chain is a special case since one scan chain only contains FFs from one clock domain. So adding delay to clock won’t cause issue. But a more general case is shown as below that one scan chain can have FFs from multiple clock domains.
If we add clock delay cells to each clock domain, we can have hold time violation in between scan sections.
To fix hold timing, generally we can add delay to data path if only a few paths have issue or adjust clock tree delay. In DFT shift mode, there is one extra way which is to add a hold-up latch to fix hold.
Hold-up latch is explained in Lock-Up Latch: Implication on Timing
Without lock-up latch, clock2 (capturing FF clock) rising edge comes later than clock1 (launching FF clock) rising edge. So there is a hold violation.
With lock-up latch, hold time can be satisfied.
But if a lock-up latch can magically fix hold, why not we introduce it to other modes like func mode? Here is why. Hold-up latch basically moves FF q toggling from clock rising edge to clock falling edge. It targets design with unlike setup timing issue and only hold issue due to clock edge miss-alignment. This is exactly scan shift mode.
Above only shows capturing clock edge comes later than launching clock edge. If this is the other way around, lock-up latch still works.
This is why in STA timing analysis, due to lock-up latch is inserted in the middle of a path, that path is not analyzed for timing anymore. Tool treats it as async path and assume no timing requirement.