In my other articles in this series, it was discussed the methodology of how to test flip-flops in multiple power domains and voltage domains. This article discusses another big factor, DFT logic itself power domain issue, in multiple power domain DFT implementation.
Let’s take a look of a simple example first. A chip comes with a DFT logic which consists of a TAP controller and several IR/DRs. TAP controller is connected to JTAG ports as expected. DRs controls lbist/mbist/etc DFT logic (not shown in diagram) which intend to test MUT (Module Under Test) customer module. DFT logic is relatively more powered on than MUT which means it is possible both DFT and MUT are on, or only DFT is on and MUT is off, but we don’t have a case that DFT is off and MUT is on. In this case, DFT implementation is straightforward and can be treated like both DFT and MUT on. In other words, DFT can be implemented like there is only one power domain and no multiple power domains.
Let’s make it more complicated and more like real case. In a typical chip design, there are multiple MUTs designed by different groups and eventually they are integrated into one chip. Chip has only one GDFT, global DFT logic, which is connected to the JTAG interface. But each MUT has its own LDFT, local DFT logic. Some benefits of local DFT logic are parallel testing of multiple MUTs, improved DFT coverage of each MUT, simplified DFT design of each MUT, and eased timing of each MUT.
Let’s assume the power domain on/off relationship is as shown that GDFT is more on than LDFT and local Function 1 (Fn1) module and LDFT/Fn1 are more on than local Fn2. In this case, DFT implementation is still straightforward and it is like all of them are in the same power domain.
BUT the wave turns if LDFT is assigned to “less_on” power domain as Fn2. If not properly treated, we are not just talking about DFT loss. We are indeed talking about non-functional chip. Next let’s see what is the issue.
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